From patchwork Wed Sep 2 08:59:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 7110011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 43BB0BEEC1 for ; Wed, 2 Sep 2015 09:04:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2486B2065D for ; Wed, 2 Sep 2015 09:04:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 20DBD20532 for ; Wed, 2 Sep 2015 09:03:59 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZX3vR-0007aV-DC; Wed, 02 Sep 2015 09:01:49 +0000 Received: from mail-yk0-f181.google.com ([209.85.160.181]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZX3vN-0007RF-Ns; Wed, 02 Sep 2015 09:01:46 +0000 Received: by ykek143 with SMTP id k143so3090445yke.2; Wed, 02 Sep 2015 02:01:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JubeSqkdEEt/0cslosvEJOtLNoK2xQDiYoRYyDgdXfA=; b=fLbRTKYSBU+7yJ6cABD9EYxA3s+iG4VWUWmViOE34va4LwLp+it3qoCTO2YZ8PJ3ac C1iTJHffnhs8LfmuznKIo1N5xr3txvjivswLYTW8betdy2PNA/xgkZy8zr3Pv8aE0vQ3 w8qMZ3PFfd6lu3ZA9+MdwU0ItMAe9QYKQ1M6D1/nEEXEHTvCx+4051aI96+V7AYScFVT ZVW7JF08Wwn0G/ne+YVzUifzVkd3NhZ6Ptf50AhZxLG404T/O0cdX50H86xsw+uYC6go BHVY96eVEzm/G7IzYEiMQWnj1g8HON45IaYLAvYdQc6BMIqxguN5G7IFgIxTwxIy8Gmk HMCg== X-Received: by 10.170.123.83 with SMTP id p80mr2561182ykb.127.1441184484627; Wed, 02 Sep 2015 02:01:24 -0700 (PDT) Received: from localhost.localdomain ([173.239.41.18]) by smtp.gmail.com with ESMTPSA id g197sm20208259ywe.4.2015.09.02.02.01.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 02 Sep 2015 02:01:24 -0700 (PDT) From: Caesar Wang To: heiko@sntech.de, khilman@linaro.org Subject: [PATCH v17 1/4] dt-bindings: add document of Rockchip power domains Date: Wed, 2 Sep 2015 16:59:37 +0800 Message-Id: <1441184380-13827-2-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441184380-13827-1-git-send-email-wxt@rock-chips.com> References: <1441184380-13827-1-git-send-email-wxt@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150902_020145_882532_2156F121 X-CRM114-Status: GOOD ( 16.07 ) X-Spam-Score: -2.4 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, ulf.hansson@linaro.org, linux@arm.linux.org.uk, arnd@arndb.de, ijc+devicetree@hellion.org.uk, "jinkun.hong" , linus.walleij@linaro.org, dmitry.torokhov@gmail.com, linux-kernel@vger.kernel.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, robh+dt@kernel.org, galak@codeaurora.org, tomasz.figa@gmail.com, mturquette@baylibre.com, linux-arm-kernel@lists.infradead.org, wxt@rock-chips.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This add the necessary binding documentation for the power domains found on Rockchip SoCs. Signed-off-by: jinkun.hong Signed-off-by: Caesar Wang --- Changes in v17: - add the decription in detail for RK3288 SoCs. Changes in v16: - remove the pmu node. Changes in v15: None Changes in v14: None Changes in v13: None Changes in v12: None Changes in v11: None Changes in v10: None Changes in v9: - add document decription. Changes in v8: - document go back to v2. Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: - DT structure has changed. Changes in v2: - move clocks to "optional". .../bindings/soc/rockchip/power_domain.txt | 114 +++++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt new file mode 100644 index 0000000..4cf6b27 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt @@ -0,0 +1,114 @@ +* Rockchip Power Domains + +Rockchip processors include support for multiple power domains which can be +powered up/down by software based on different application scenes to save power. + +Required properties for power domain controller: +- compatible: Should be one of the following. + "rockchip,rk3288-power-controller" - for RK3288 SoCs. +- #power-domain-cells: Number of cells in a power-domain specifier. + Should be 1 for multiple PM domains. +- #address-cells: Should be 1. +- #size-cells: Should be 0. + +Required properties for power domain sub nodes: +- reg: index of the power domain, should use macros in: + "include/dt-bindings/power-domain/rk3288.h" - for RK3288 type power domain. +- clocks (optional): phandles to clocks which need to be enabled while power domain + switches state. + +Example: + + power: power-controller { + compatible = "rockchip,rk3288-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_gpu { + reg = ; + clocks = <&cru ACLK_GPU>; + }; + }; + +Node of a device using power domains must have a power-domains property, +containing a phandle to the power device node and an index specifying which +power domain to use. +The index should use macros in: + "include/dt-bindings/power-domain/rk3288.h" - for rk3288 type power domain. + +Example of the node using power domain: + + node { + /* ... */ + power-domains = <&power RK3288_PD_GPU>; + /* ... */ + }; + +Others, all the device clocks being listed in the power-domains itself. +All the device clocks are included in someone domians that need to enable +before you operate them. + +As the chip designs for PM hardware. We need turn on the noc clocks, +if we are operating the "pd_vio" domain to enter the idle status. + +As the following described in detail for every device be included in domains +on RK3288 SoCs. + + /* GPU's ACLK_GPU on the ACLK_GPU_NIU */ + pd_gpu { + reg = ; + clocks = <&cru ACLK_GPU>; + }; + + /* HEVC AXI clocks */ + pd_hevc { + reg = ; + clocks = <&cru ACLK_HEVC>, + <&cru SCLK_HEVC_CABAC>, + <&cru SCLK_HEVC_CORE>, + <&cru HCLK_HEVC>; + }; + + /* + * RGA, VOP, MIPI, LVDS, EDP..., says the ACLK* on the ACLK_VIO_NIU, + * others are on the HCLK_VIO_NIU. + */ + pd_vio { + reg = ; + clocks = <&cru ACLK_IEP>, + <&cru ACLK_ISP>, + <&cru ACLK_RGA>, + <&cru ACLK_VIP>, + <&cru ACLK_VOP0>, + <&cru ACLK_VOP1>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru HCLK_IEP>, + <&cru HCLK_ISP>, + <&cru HCLK_RGA>, + <&cru HCLK_VIP>, + <&cru HCLK_VOP0>, + <&cru HCLK_VOP1>, + <&cru PCLK_EDP_CTRL>, + <&cru PCLK_HDMI_CTRL>, + <&cru PCLK_LVDS_PHY>, + <&cru PCLK_MIPI_CSI>, + <&cru PCLK_MIPI_DSI0>, + <&cru PCLK_MIPI_DSI1>, + <&cru SCLK_EDP_24M>, + <&cru SCLK_EDP>, + <&cru SCLK_ISP_JPE>, + <&cru SCLK_ISP>, + <&cru SCLK_RGA>; + }; + + /* + * Video's ACLK_VCODEC on the ACLK_VCODEC_NIU, Video's HCLK_VCODEC, + * on the HCLK_VCODEC_NIU. + */ + pd_video { + reg = ; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + };