From patchwork Thu Sep 10 08:37:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 7152521 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E156D9F326 for ; Thu, 10 Sep 2015 08:44:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F29DD2041E for ; Thu, 10 Sep 2015 08:44:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F0C2920836 for ; Thu, 10 Sep 2015 08:44:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZZxRU-0003dU-Qu; Thu, 10 Sep 2015 08:42:52 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZZxOE-0006WC-Kq for linux-arm-kernel@lists.infradead.org; Thu, 10 Sep 2015 08:39:32 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t8A8d3RQ005566; Thu, 10 Sep 2015 03:39:03 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t8A8d3Id009872; Thu, 10 Sep 2015 03:39:03 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.224.2; Thu, 10 Sep 2015 03:38:54 -0500 Received: from dlep32.itg.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t8A8bqLA018732; Thu, 10 Sep 2015 03:38:59 -0500 From: Peter Ujfalusi To: , , Subject: [PATCH 21/21] dmaengine: edma: Simplify and optimize ccerr interrupt handler Date: Thu, 10 Sep 2015 11:37:50 +0300 Message-ID: <1441874270-2399-22-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1441874270-2399-1-git-send-email-peter.ujfalusi@ti.com> References: <1441874270-2399-1-git-send-email-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150910_013931_076417_3E6148E8 X-CRM114-Status: GOOD ( 13.03 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arnd@arndb.de, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, olof@lixom.net, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP No need to run through the bits in QEMR and CCERR events since they will not trigger any action, so just clearing the errors there is fine. In case of the missed event the loop can be optimized so we spend less time to handle the event. Signed-off-by: Peter Ujfalusi --- drivers/dma/edma.c | 64 ++++++++++++++++++++---------------------------------- 1 file changed, 23 insertions(+), 41 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index f1e898525ae6..81302daf687c 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1625,6 +1625,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) int i; int ctlr; unsigned int cnt = 0; + unsigned int val; ctlr = ecc->id; if (ctlr < 0) @@ -1637,54 +1638,35 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) while (1) { int j = -1; - if (edma_read_array(ecc, EDMA_EMR, 0)) + if ((val = edma_read_array(ecc, EDMA_EMR, 0))) j = 0; - else if (edma_read_array(ecc, EDMA_EMR, 1)) + else if ((val = edma_read_array(ecc, EDMA_EMR, 1))) j = 1; if (j >= 0) { - dev_dbg(ecc->dev, "EMR%d %08x\n", j, - edma_read_array(ecc, EDMA_EMR, j)); - for (i = 0; i < 32; i++) { + unsigned long emr = val; + + dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); + for (i = find_next_bit(&emr, 32, 0); i < 32; + i = find_next_bit(&emr, 32, i + 1)) { int k = (j << 5) + i; - if (edma_read_array(ecc, EDMA_EMR, j) & - BIT(i)) { - /* Clear the corresponding EMR bits */ - edma_write_array(ecc, EDMA_EMCR, j, + /* Clear the corresponding EMR bits */ + edma_write_array(ecc, EDMA_EMCR, j, BIT(i)); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, j, BIT(i)); - /* Clear any SER */ - edma_shadow0_write_array(ecc, SH_SECR, - j, BIT(i)); - edma_error_handler(&ecc->slave_chans[k]); - } - } - } else if (edma_read(ecc, EDMA_QEMR)) { - dev_dbg(ecc->dev, "QEMR %02x\n", - edma_read(ecc, EDMA_QEMR)); - for (i = 0; i < 8; i++) { - if (edma_read(ecc, EDMA_QEMR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ecc, EDMA_QEMCR, BIT(i)); - edma_shadow0_write(ecc, SH_QSECR, - BIT(i)); - - /* NOTE: not reported!! */ - } - } - } else if (edma_read(ecc, EDMA_CCERR)) { - dev_dbg(ecc->dev, "CCERR %08x\n", - edma_read(ecc, EDMA_CCERR)); - /* FIXME: CCERR.BIT(16) ignored! much better - * to just write CCERRCLR with CCERR value... - */ - for (i = 0; i < 8; i++) { - if (edma_read(ecc, EDMA_CCERR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ecc, EDMA_CCERRCLR, BIT(i)); - - /* NOTE: not reported!! */ - } + edma_error_handler(&ecc->slave_chans[k]); } + } else if ((val = edma_read(ecc, EDMA_QEMR))) { + dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); + /* Not reported, just clear the interrupt reason. */ + edma_write(ecc, EDMA_QEMCR, val); + edma_shadow0_write(ecc, SH_QSECR, val); + } else if ((val = edma_read(ecc, EDMA_CCERR))) { + dev_warn(ecc->dev, "CCERR 0x%08x\n", val); + /* Not reported, just clear the interrupt reason. */ + edma_write(ecc, EDMA_CCERRCLR, val); } + if (!edma_error_pending(ecc)) break; cnt++;