From patchwork Fri Sep 18 08:51:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 7214121 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 681A2BEEC1 for ; Fri, 18 Sep 2015 08:53:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 83236207A4 for ; Fri, 18 Sep 2015 08:53:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 93FB0208D6 for ; Fri, 18 Sep 2015 08:53:47 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcrOz-0001RO-Aj; Fri, 18 Sep 2015 08:52:17 +0000 Received: from mail-pa0-f45.google.com ([209.85.220.45]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcrOf-0000oc-1H; Fri, 18 Sep 2015 08:52:01 +0000 Received: by padhy16 with SMTP id hy16so45725538pad.1; Fri, 18 Sep 2015 01:51:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AB/jDdNJCtOARaP72GbmmEKKf07ElmuMtCdBw6oVIAo=; b=cFMtFIeeKKlF1goaOKiMVVdCPYqNEi8q5821hS2vRpwzwDEApwUG00abIdO9qgyfIP uGy7B6cslVscJ2nkbFQxC85SPlp3Vczv9j7Pf6V3tUXLKZL+AF2IWCxYpAO8pI23kzmr eztCNBDNsoYp+gWS7RTeKTibwb6WS0BXViFxhUXt/iqoDQMlseW+XA5IwUemC62QFI1/ oXGl6lOlJ2ilPFTm3CDfX1FQ+5axeZFPZybf7u6crvY9mNfXXsoUj8MBrJvm276WzUEh UUSMneGBJ7zWewtPlVb+YqNLJ/vKvULvayM8AloH171i+sMmO1qMIyDiWXbJlIAP4NGf +cLQ== X-Received: by 10.67.6.164 with SMTP id cv4mr5949622pad.59.1442566296302; Fri, 18 Sep 2015 01:51:36 -0700 (PDT) Received: from localhost.localdomain ([103.46.142.38]) by smtp.gmail.com with ESMTPSA id fd9sm7699307pab.34.2015.09.18.01.51.30 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Sep 2015 01:51:35 -0700 (PDT) From: Caesar Wang To: heiko@sntech.de, daniel.lezcano@linaro.org, will.deacon@arm.com, catalin.marinas@arm.com Subject: [PATCH v1 1/3] clocksource: rockchip: Make the driver more readability and compatible Date: Fri, 18 Sep 2015 16:51:09 +0800 Message-Id: <1442566271-10695-2-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442566271-10695-1-git-send-email-wxt@rock-chips.com> References: <1442566271-10695-1-git-send-email-wxt@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150918_015157_383141_138FE580 X-CRM114-Status: GOOD ( 14.42 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, olof@lixom.net, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, Caesar Wang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Build the arm64 SoCs (e.g.: RK3368) on Rockchip platform, There are some failure with build up on timer driver for rockchip. logs: ... drivers/clocksource/rockchip_timer.c:156:13: error: 'NO_IRQ' undeclared /tmp/ccdAnNy5.s:47: Error: missing immediate expression at operand 1 -- `dsb` ... The problem was different semantics of dsb on btw arm32 and arm64, Here we can convert the dsb with insteading of dsb(sy). NO_IRQ definition is missing for ARM64, since NO_IRQ being -1 is a legacy thing for ARM - all ARM drivers are supposed to be converted to use <= 0 or == 0 to detect invalid IRQs, and _eventually_ once all users are gone, NO_IRQ deleted. Modern drivers should _all_ be using !irq to detect invalid IRQs, and not using NO_IRQ. Meanwhile, I change a bit to make the code more readability for driver when I check the code style. Signed-off-by: Caesar Wang --- Changes in v1: - As Russell, Thomas, Daniel comments, let's replace NO_IRQ by '!irq'. drivers/clocksource/rockchip_timer.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c index bb2c2b0..e1af449 100644 --- a/drivers/clocksource/rockchip_timer.c +++ b/drivers/clocksource/rockchip_timer.c @@ -17,16 +17,16 @@ #define TIMER_NAME "rk_timer" -#define TIMER_LOAD_COUNT0 0x00 -#define TIMER_LOAD_COUNT1 0x04 -#define TIMER_CONTROL_REG 0x10 -#define TIMER_INT_STATUS 0x18 +#define TIMER_LOAD_COUNT0 0x00 +#define TIMER_LOAD_COUNT1 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_INT_STATUS 0x18 -#define TIMER_DISABLE 0x0 -#define TIMER_ENABLE 0x1 -#define TIMER_MODE_FREE_RUNNING (0 << 1) -#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1) -#define TIMER_INT_UNMASK (1 << 2) +#define TIMER_DISABLE (0 << 0) +#define TIMER_ENABLE (1 << 0) +#define TIMER_MODE_FREE_RUNNING (0 << 1) +#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1) +#define TIMER_INT_UNMASK (1 << 2) struct bc_timer { struct clock_event_device ce; @@ -49,14 +49,14 @@ static inline void __iomem *rk_base(struct clock_event_device *ce) static inline void rk_timer_disable(struct clock_event_device *ce) { writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG); - dsb(); + dsb(sy); } static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags) { writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags, rk_base(ce) + TIMER_CONTROL_REG); - dsb(); + dsb(sy); } static void rk_timer_update_counter(unsigned long cycles, @@ -64,13 +64,13 @@ static void rk_timer_update_counter(unsigned long cycles, { writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0); writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1); - dsb(); + dsb(sy); } static void rk_timer_interrupt_clear(struct clock_event_device *ce) { writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS); - dsb(); + dsb(sy); } static inline int rk_timer_set_next_event(unsigned long cycles, @@ -148,7 +148,7 @@ static void __init rk_timer_init(struct device_node *np) bc_timer.freq = clk_get_rate(timer_clk); irq = irq_of_parse_and_map(np, 0); - if (irq == NO_IRQ) { + if (!irq) { pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME); return; } @@ -173,4 +173,5 @@ static void __init rk_timer_init(struct device_node *np) clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX); } + CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", rk_timer_init);