From patchwork Fri Sep 18 16:26:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 7218951 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9FD099F372 for ; Fri, 18 Sep 2015 16:30:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 461B620850 for ; Fri, 18 Sep 2015 16:30:06 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4DA5C20918 for ; Fri, 18 Sep 2015 16:30:05 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcyWQ-0002pL-0p; Fri, 18 Sep 2015 16:28:26 +0000 Received: from merlin.infradead.org ([205.233.59.134]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcyVi-00023v-RP for linux-arm-kernel@bombadil.infradead.org; Fri, 18 Sep 2015 16:27:42 +0000 Received: from mail-pa0-f49.google.com ([209.85.220.49]) by merlin.infradead.org with esmtps (Exim 4.85 #2 (Red Hat Linux)) id 1ZcyVg-0001Rn-Kg for linux-arm-kernel@lists.infradead.org; Fri, 18 Sep 2015 16:27:41 +0000 Received: by padhk3 with SMTP id hk3so55053824pad.3 for ; Fri, 18 Sep 2015 09:27:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/VlSids3HYGmneDewl1GbbMuz9FYMsHoltPsaVL/Nhg=; b=gf/q9/CNklisc45SDBSeT5Y9jjromfJVXip6juId9psbDeCfp0TJQye9TZxoe58TMR k/mECjX7zsYJ1R1A0GoW3P0Ssb5ERt+alEo0tjkb6ih4CacWos8RP/nFa3pnHgzJY84I LWG4AKXYMZO8VQwtPOSeM5BzujH2oFCuTPTcHcO3rDw8G4t0L0Kq3N66PzJKDITOcR89 q2ujrYDa8BOlCeEei43J2I6f6vVgN2Ql8692NZXVyhvg9QELKYiI0HIf77f7B6LN2+Od a+a9IcayyjWC/HUzjo4pZ7pRsaj2SukB59gqzBBiEGOYP2BhW9GUL7PGQjMF7eqdekQu bnnQ== X-Gm-Message-State: ALoCoQlpPTtl1uKs7gSSf3AkwxdWHwZq8YU01471hQ6edznfupSw5f/rrarmH6XHMU8ce46XyN2O X-Received: by 10.66.65.234 with SMTP id a10mr8228136pat.2.1442593644261; Fri, 18 Sep 2015 09:27:24 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id la4sm9847027pbc.76.2015.09.18.09.27.22 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Sep 2015 09:27:23 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net Subject: [RFC PATCH 16/20] coresight: etm-perf: implementing trace related APIs Date: Fri, 18 Sep 2015 10:26:30 -0600 Message-Id: <1442593594-10665-17-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> References: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150918_122740_749027_04DF9CFF X-CRM114-Status: GOOD ( 17.54 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, pawel.moll@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, adrian.hunter@intel.com, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Implementing the API that connect trace control, i.e initiation and termination, to the Perf core. That way trace collection can be started when the process it is associated to is executed by a CPU, and stopped when yanked away. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm-perf.c | 97 ++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 3aeb4215bb22..edacf4b1d0bc 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -30,6 +30,7 @@ static struct pmu etm_pmu; +static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle); static DEFINE_PER_CPU(struct coresight_device *, csdev_src); static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); @@ -248,6 +249,98 @@ static void etm_free_aux(void *data) kfree(data); } +static void etm_event_stop(struct perf_event *event, int mode) +{ + int cpu = smp_processor_id(); + struct coresight_device *src = per_cpu(csdev_src, cpu); + struct coresight_device *sink = per_cpu(csdev_sink, cpu); + + if (event->hw.state == PERF_HES_STOPPED) + return; + + if (!src || !sink) + return; + + /* stop tracer */ + if (source_ops(src)->trace_enable(src, false)) + return; + + /* tell the core */ + event->hw.state = PERF_HES_STOPPED; + + + if (mode & PERF_EF_UPDATE) { + struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle); + + if (WARN_ON_ONCE(handle->event != event)) + return; + + /* update trace information */ + sink_ops(sink)->update_buffer(sink, handle); + } +} + +static void etm_event_start(struct perf_event *event, int flags) +{ + int cpu = smp_processor_id(); + struct coresight_device *csdev = per_cpu(csdev_src, cpu); + + if (!csdev) + goto fail; + + /* tell the perf core the event is alive */ + event->hw.state = 0; + + if (source_ops(csdev)->trace_enable(csdev, true)) + goto fail; + + return; + +fail: + event->hw.state = PERF_HES_STOPPED; +} + +static void etm_event_del(struct perf_event *event, int mode) +{ + int cpu = smp_processor_id(); + struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle); + struct coresight_device *csdev = per_cpu(csdev_sink, cpu); + + if (!csdev) + return; + + etm_event_stop(event, PERF_EF_UPDATE); + sink_ops(csdev)->unset_buffer(csdev, handle); +} + +static int etm_event_add(struct perf_event *event, int mode) +{ + int ret, cpu = smp_processor_id(); + struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle); + struct hw_perf_event *hwc = &event->hw; + struct coresight_device *csdev = per_cpu(csdev_sink, cpu); + + if (!csdev) + return -EINVAL; + + if (handle->event) + return -EBUSY; + + ret = sink_ops(csdev)->set_buffer(csdev, event, handle); + if (ret) + return ret; + + if (mode & PERF_EF_START) { + etm_event_start(event, 0); + if (hwc->state & PERF_HES_STOPPED) { + etm_event_del(event, 0); + return -EBUSY; + } + } + + return 0; +} + static int __init etm_perf_init(void) { etm_pmu.capabilities = PERF_PMU_CAP_EXCLUSIVE; @@ -258,6 +351,10 @@ static int __init etm_perf_init(void) etm_pmu.event_init = etm_event_init; etm_pmu.setup_aux = etm_setup_aux; etm_pmu.free_aux = etm_free_aux; + etm_pmu.stop = etm_event_stop; + etm_pmu.start = etm_event_start; + etm_pmu.del = etm_event_del; + etm_pmu.add = etm_event_add; return perf_pmu_register(&etm_pmu, CORESIGHT_ETM_PMU_NAME, -1); }