From patchwork Fri Sep 18 16:26:32 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 7219221 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1BE789F32B for ; Fri, 18 Sep 2015 16:45:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 33C7C20870 for ; Fri, 18 Sep 2015 16:45:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 45CBC20859 for ; Fri, 18 Sep 2015 16:45:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcylN-0003v2-OT; Fri, 18 Sep 2015 16:43:53 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zcykr-0002XH-CD for linux-arm-kernel@bombadil.infradead.org; Fri, 18 Sep 2015 16:43:21 +0000 Received: from mail-pa0-f48.google.com ([209.85.220.48]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcyVp-0006xO-7p for linux-arm-kernel@lists.infradead.org; Fri, 18 Sep 2015 16:27:50 +0000 Received: by padhy16 with SMTP id hy16so55274298pad.1 for ; Fri, 18 Sep 2015 09:27:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=i4spHBhuAtMbI22/X1FsXnNk+dq+t5nTkeBtWtrKcfA=; b=GN+o7XMeo/S71aMbNhDjlSP3cGq6d3Ff24qrX2MiovUylseu5NJwA/RtOnqUIH5h5S jEuBwZrLoB/XcRACzXpSbuGOStf6Pem5t+KSwyC4YGJeYPBT2lhumq1rGva0re6p+Tho cmSljcZXUnuNobqTfJSVgf4BclaMUrIWPgaAoUwqYWsFgXDNbfH8z0vxC3XPtdBiOK7Z Hn74es2xLYkbc1KRZycEseqL8Jqd9RqR9QT88+PFCfzsfQxM/qsCn1nvacFYkVdxOPRd +Zl48Z10XXL1Fv9AdyHpi8E00cVRPCkUvol0EYCxWUs6jIzJ3pHrRjiRCdxRaPM46I+D ttsg== X-Gm-Message-State: ALoCoQk0C0/b95Q31xv0WRWJ02DKjVDub5FNK+XnMLbSMhbrLbAyAO1rgdGBzQSuCRRGhidqdfJF X-Received: by 10.68.237.161 with SMTP id vd1mr7938642pbc.168.1442593647191; Fri, 18 Sep 2015 09:27:27 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id la4sm9847027pbc.76.2015.09.18.09.27.25 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Sep 2015 09:27:26 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net Subject: [RFC PATCH 18/20] coresight: etm3x: pushing down perf configuration to tracer Date: Fri, 18 Sep 2015 10:26:32 -0600 Message-Id: <1442593594-10665-19-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> References: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150918_172749_423807_A66C0A09 X-CRM114-Status: GOOD ( 20.02 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, pawel.moll@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, adrian.hunter@intel.com, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The perf command line tool supports configuration for cycle accurate and timestamps. Configuration for those field is found in the 'config' field of the event configuration attributes. Since the bit fields were organised to match, the only thing that is needed is to make sure no extra fields were set. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm-perf.c | 12 +++++------ drivers/hwtracing/coresight/coresight-etm3x.c | 27 +++++++++++++++++++++++- include/linux/coresight.h | 3 ++- 3 files changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index de0198e72603..a662842f3327 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -122,7 +122,7 @@ out: return ret; } -static int etm_event_config_single_source(int source) +static int etm_event_config_single_source(int source, struct perf_event *event) { struct coresight_device *csdev; @@ -134,10 +134,10 @@ static int etm_event_config_single_source(int source) if (csdev->type != CORESIGHT_DEV_TYPE_SOURCE) return -EINVAL; - return source_ops(csdev)->configure(csdev); + return source_ops(csdev)->configure(csdev, event); } -static int etm_event_config_sources(int source) +static int etm_event_config_sources(int source, struct perf_event *event) { int cpu, ret; @@ -147,13 +147,13 @@ static int etm_event_config_sources(int source) /* source == -1 is for all CPUs. */ if (source != -1) { /* configure one source */ - ret = etm_event_config_single_source(source); + ret = etm_event_config_single_source(source, event); goto out; } /* same process as above, but for all CPUs */ for_each_online_cpu(cpu) { - ret = etm_event_config_single_source(cpu); + ret = etm_event_config_single_source(cpu, event); if (ret) goto reset; } @@ -220,7 +220,7 @@ static int etm_event_init(struct perf_event *event) if (ret) goto out; - ret = etm_event_config_sources(event->cpu); + ret = etm_event_config_sources(event->cpu, event); event->destroy = etm_event_destroy; out: diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 6a44ea330a4a..077b49714259 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -313,6 +313,25 @@ static void etm_power_down(struct coresight_device *csdev) pm_runtime_put(csdev->dev.parent); } +#define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN) + +static int etm_parse_event_config(struct etm_drvdata *drvdata, + struct perf_event *event) +{ + u64 config = event->attr.config; + + /* + * At this time only cycle accurate and timestamp options are + * available. As such clear everything else that may have been + * configured and set the ETM control register based on what was + * requested. + */ + config &= ETM3X_SUPPORTED_OPTIONS; + drvdata->ctrl = config; + + return 0; +} + /** * etm_configure_cpu - configure ETM registers * @csdev - the etm that needs to be configure. @@ -334,6 +353,8 @@ static void etm_configure_cpu(void *info) etm_set_prog(drvdata); etmcr = etm_readl(drvdata, ETMCR); + /* Clear setting from a previous run if need be */ + etmcr &= ~ETM3X_SUPPORTED_OPTIONS; etmcr |= drvdata->port_size; etmcr |= ETMCR_ETM_EN; etm_writel(drvdata, drvdata->ctrl | etmcr, ETMCR); @@ -379,10 +400,14 @@ static void etm_configure_cpu(void *info) CS_LOCK(drvdata->base); } -static int etm_configure(struct coresight_device *csdev) +static int etm_configure(struct coresight_device *csdev, + struct perf_event *event) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + if (etm_parse_event_config(drvdata, event)) + return -EINVAL; + return smp_call_function_single(drvdata->cpu, etm_configure_cpu, csdev, 1); } diff --git a/include/linux/coresight.h b/include/linux/coresight.h index da76b2951f10..e1a14c84082f 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -237,7 +237,8 @@ struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); int (*trace_id)(struct coresight_device *csdev); bool (*is_enabled)(struct coresight_device *csdev); - int (*configure)(struct coresight_device *csdev); + int (*configure)(struct coresight_device *csdev, + struct perf_event *event); int (*trace_enable)(struct coresight_device *csdev, bool enable); int (*enable)(struct coresight_device *csdev); void (*disable)(struct coresight_device *csdev);