From patchwork Fri Sep 18 16:26:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 7219031 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 052379F372 for ; Fri, 18 Sep 2015 16:31:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7BE5C20878 for ; Fri, 18 Sep 2015 16:31:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 963EB20903 for ; Fri, 18 Sep 2015 16:31:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcyXd-0004K5-MS; Fri, 18 Sep 2015 16:29:41 +0000 Received: from mail-pa0-f53.google.com ([209.85.220.53]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcyVp-0001jz-JQ for linux-arm-kernel@lists.infradead.org; Fri, 18 Sep 2015 16:27:51 +0000 Received: by padhk3 with SMTP id hk3so55055151pad.3 for ; Fri, 18 Sep 2015 09:27:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LPXBZ7TnDMEYAZBhGrXKbPFANTJy2sUK47t/3DqtoQ4=; b=ZNLB9womqq1r3/gKruG7uJFBH3j9QXlUXeV/YSDg/IcZigGrTq96C1JpMHp3EZL+C6 66x5ua9w5gwjJgahmPuKi+FC5KtfvaeetN3naI52bDuzDMBD9lJEVpzxOM72c802necP iRC/va8LQqG2KF+CxKDS9xMp8gER5qJ1BSeZut1vN98oR1JGs2x2nip2CJ5tZLGx+OoV D8GN6NtbW/qSUpY+/KD/h7Mgsj8rsZM6jUobqqsUe8X5SjphwpWPe3c0In+GIyxzEIVT ttB+pWuER3uuo/MwEGv63m6onUf02Ex34dA3EjvYs6MZUo1zezQTiv9nNJ3pCT+bv/8q oBTA== X-Gm-Message-State: ALoCoQnKIMzxMSyM54RL6ZgiuOYxZImIQVCsvAQihJxXdb9++qz0jX/uGENPt+5vgqFXeman9sIi X-Received: by 10.68.230.33 with SMTP id sv1mr8313244pbc.160.1442593648815; Fri, 18 Sep 2015 09:27:28 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id la4sm9847027pbc.76.2015.09.18.09.27.27 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Sep 2015 09:27:28 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net Subject: [RFC PATCH 19/20] coresight: etm3x: implementing perf's user/kernel mode Date: Fri, 18 Sep 2015 10:26:33 -0600 Message-Id: <1442593594-10665-20-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> References: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150918_092749_908646_A3B03403 X-CRM114-Status: GOOD ( 14.73 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, pawel.moll@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, adrian.hunter@intel.com, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Configure tracers in accordance with the specification conveyed by the perf cmd line tool. For example if only user space is requested, configure the address range comparator with the kerne's address range and set the 'exclude' bit, which will result in tracing everything except the kernel. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm3x.c | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 077b49714259..2f818dbde099 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -320,6 +320,41 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, { u64 config = event->attr.config; + if (event->attr.exclude_kernel || event->attr.exclude_user) { + u32 event_encoding; + u32 flags = (1 << 0 | /* instruction execute*/ + 3 << 3 | /* ARM instruction */ + 0 << 5 | /* No data value comparison */ + 0 << 7 | /* No exact mach */ + 0 << 8 | /* Ignore context ID */ + 0 << 10); /* Security ignored */ + + /* Bit 0 is address range comparator 1 */ + drvdata->enable_ctrl1 = ETMTECR1_ADDR_COMP_1; + + /* Bit 24 controls whether the address range should be + * included or excluded. + */ + if (event->attr.exclude_kernel) + drvdata->enable_ctrl1 |= BIT(24); + + /* No need to worry about single address comparators */ + drvdata->enable_ctrl2 = 0x0; + + drvdata->addr_val[0] = (u32) _stext; + drvdata->addr_val[1] = (u32) _etext; + drvdata->addr_acctype[0] = flags; + drvdata->addr_acctype[1] = flags; + drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE; + drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE; + + event_encoding = 0x00 << 14 | /* Boolean function select A */ + 0x01 << 4 | /* Addr range comparator 0-7 */ + 0x00 << 0; /* Addr range comparator 1 */ + + drvdata->enable_event = event_encoding; + } + /* * At this time only cycle accurate and timestamp options are * available. As such clear everything else that may have been @@ -362,6 +397,7 @@ static void etm_configure_cpu(void *info) etm_writel(drvdata, drvdata->startstop_ctrl, ETMTSSCR); etm_writel(drvdata, drvdata->enable_event, ETMTEEVR); etm_writel(drvdata, drvdata->enable_ctrl1, ETMTECR1); + etm_writel(drvdata, drvdata->enable_ctrl2, ETMTECR2); etm_writel(drvdata, drvdata->fifofull_level, ETMFFLR); for (i = 0; i < drvdata->nr_addr_cmp; i++) { etm_writel(drvdata, drvdata->addr_val[i], ETMACVRn(i));