From patchwork Fri Sep 18 16:26:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 7218921 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D7B709F380 for ; Fri, 18 Sep 2015 16:29:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E9AA82091C for ; Fri, 18 Sep 2015 16:29:38 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ED39220903 for ; Fri, 18 Sep 2015 16:29:36 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcyVv-0002IE-62; Fri, 18 Sep 2015 16:27:55 +0000 Received: from mail-pa0-f43.google.com ([209.85.220.43]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcyVX-0001RB-8J for linux-arm-kernel@lists.infradead.org; Fri, 18 Sep 2015 16:27:32 +0000 Received: by pacex6 with SMTP id ex6so55402713pac.0 for ; Fri, 18 Sep 2015 09:27:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=43gRpp+Ocippf1GPvijnKiQU85urok+GkYyinYLZe9o=; b=CqcCEexEG6GXodla5EdbsZS2eZURFBrUFJ2rXA03f2QZ2iq6cWxA4hs7w0s19vPioy UmYIt5AzgzCgGtTKQtK2jMBW+5271kxWXMnw1/0rD6Tp/1AwGyz+BEIHNfrAGsPhc6AQ 2VNliAbgxc70mGj5LkHMzZxCE9QqyYm+Y1hHlxGt+EAleQkQbmrqz/+xSmv8MrhAOOcf g7ESV73xePkN69IzvNlbkViMCA7zrekTOrQPmBA0gRMMdPYcFOLcTWy0GcrfwzOwsfi7 N8JrXki7EIpQV9r0oFTNCTHApW1ZswsOH3+FMAMnajjgduWwCzBAvQHpI7+znsrUTNeK GB2g== X-Gm-Message-State: ALoCoQnXsebFxIHCN1BOtOadL2B3ZRlnAmkpy1xgil/OE65VsHHOXqPluj5gb7K3cy9hFkuTKNR3 X-Received: by 10.68.237.161 with SMTP id vd1mr7937479pbc.168.1442593629127; Fri, 18 Sep 2015 09:27:09 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id la4sm9847027pbc.76.2015.09.18.09.27.07 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Sep 2015 09:27:08 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net Subject: [RFC PATCH 05/20] coresight: etm3x: adapting default tracer setting for perf Date: Fri, 18 Sep 2015 10:26:19 -0600 Message-Id: <1442593594-10665-6-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> References: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150918_092731_474868_61E143A0 X-CRM114-Status: GOOD ( 15.45 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, pawel.moll@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, adrian.hunter@intel.com, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The perf command line tool has options to trace in kernel or user space mode. As such configuring tracers to trace the entire address range, leaving to the perf mechanic the task of collecting traces in accordance with the requested mode. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm.h | 2 ++ drivers/hwtracing/coresight/coresight-etm3x.c | 36 +++++++++++---------------- 2 files changed, 17 insertions(+), 21 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index b4481eb29304..b149a565bc32 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -165,6 +165,7 @@ * @startstop_ctrl: setting for register ETMTSSCR. * @enable_event: setting for register ETMTEEVR. * @enable_ctrl1: setting for register ETMTECR1. + * @enable_ctrl2: setting for register ETMTECR2. * @fifofull_level: setting for register ETMFFLR. * @addr_idx: index for the address comparator selection. * @addr_val: value for address comparator register. @@ -219,6 +220,7 @@ struct etm_drvdata { u32 startstop_ctrl; u32 enable_event; u32 enable_ctrl1; + u32 enable_ctrl2; u32 fifofull_level; u8 addr_idx; u32 addr_val[ETM_MAX_ADDR_CMP]; diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 3cdf0bcddb41..c6880c1ade55 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -220,6 +220,17 @@ static void etm_set_default(struct etm_drvdata *drvdata) int i; drvdata->trigger_event = ETM_DEFAULT_EVENT_VAL; + /* + * Taken verbatim from the TRM: + * + * To trace all memory: + * set bit [24] in register 0x009, the ETMTECR1, to 1 + * set all other bits in register 0x009, the ETMTECR1, to 0 + * set all bits in register 0x007, the ETMTECR2, to 0 + * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). + */ + drvdata->enable_ctrl1 = BIT(24); + drvdata->enable_ctrl2 = 0x0; drvdata->enable_event = ETM_HARD_WIRE_RES_A; drvdata->seq_12_event = ETM_DEFAULT_EVENT_VAL; @@ -1881,7 +1892,7 @@ static void etm_init_arch_data(void *info) CS_LOCK(drvdata->base); } -static void etm_init_default_data(struct etm_drvdata *drvdata) +static void etm_init_trace_id(struct etm_drvdata *drvdata) { /* * A trace ID of value 0 is invalid, so let's start at some @@ -1889,13 +1900,6 @@ static void etm_init_default_data(struct etm_drvdata *drvdata) */ static int etm3x_traceid = 0x10; - u32 flags = (1 << 0 | /* instruction execute*/ - 3 << 3 | /* ARM instruction */ - 0 << 5 | /* No data value comparison */ - 0 << 7 | /* No exact mach */ - 0 << 8 | /* Ignore context ID */ - 0 << 10); /* Security ignored */ - /* * Initial configuration only - guarantees sources handled by * this driver have a unique ID at startup time but not between @@ -1903,18 +1907,6 @@ static void etm_init_default_data(struct etm_drvdata *drvdata) * framework. */ drvdata->traceid = etm3x_traceid++; - drvdata->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN); - drvdata->enable_ctrl1 = ETMTECR1_ADDR_COMP_1; - if (drvdata->nr_addr_cmp >= 2) { - drvdata->addr_val[0] = (u32) _stext; - drvdata->addr_val[1] = (u32) _etext; - drvdata->addr_acctype[0] = flags; - drvdata->addr_acctype[1] = flags; - drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE; - drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE; - } - - etm_set_default(drvdata); } static int etm_probe(struct amba_device *adev, const struct amba_id *id) @@ -1985,7 +1977,9 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) ret = -EINVAL; goto err_arch_supported; } - etm_init_default_data(drvdata); + + etm_init_trace_id(drvdata); + etm_set_default(drvdata); desc->type = CORESIGHT_DEV_TYPE_SOURCE; desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;