diff mbox

[v2,4/9] ARM: dts: Put Cygnus core components under core bus

Message ID 1442611454-16331-5-git-send-email-rjui@broadcom.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ray Jui Sept. 18, 2015, 9:24 p.m. UTC 
Put all Cygnus core components into "core" node of type "simple-bus" in
bcm-cygnus.dtsi

Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/boot/dts/bcm-cygnus.dtsi | 54 ++++++++++++++++++++++-----------------
 1 file changed, 30 insertions(+), 24 deletions(-)

Comments

Arnd Bergmann Sept. 18, 2015, 9:30 p.m. UTC | #1 
On Friday 18 September 2015 14:24:09 Ray Jui wrote:
> 
> +       core {
> +               compatible = "simple-bus";
> +               ranges;
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +
> +               timer@19020200 {
> +                       compatible = "arm,cortex-a9-global-timer";
> +                       reg = <0x19020200 0x100>;
> +                       interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&periph_clk>;
> +               };
> +
> +               gic: interrupt-controller@19021000 {
> 

Could it be that all 'core' components are in the 0x19xxxxxx address range?
If so, please set up an appropriate ranges property for the bus. Also
add the address field for the bus according to which addresses are routed
to it.

	Arnd
Ray Jui Sept. 18, 2015, 9:57 p.m. UTC | #2 
On 9/18/2015 2:30 PM, Arnd Bergmann wrote:
> On Friday 18 September 2015 14:24:09 Ray Jui wrote:
>>
>> +       core {
>> +               compatible = "simple-bus";
>> +               ranges;
>> +               #address-cells = <1>;
>> +               #size-cells = <1>;
>> +
>> +               timer@19020200 {
>> +                       compatible = "arm,cortex-a9-global-timer";
>> +                       reg = <0x19020200 0x100>;
>> +                       interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> +                       clocks = <&periph_clk>;
>> +               };
>> +
>> +               gic: interrupt-controller@19021000 {
>>
> 
> Could it be that all 'core' components are in the 0x19xxxxxx address range?
> If so, please set up an appropriate ranges property for the bus. Also
> add the address field for the bus according to which addresses are routed
> to it.
> 
> 	Arnd
> 

Yes all 'core' components are in the 0x19xxxxx address range for Cygnus.
It's fine and makes sense to set up proper ranges for this bus. But I
might have some issues with the 'soc' components and the 'soc' bus,
which I'll explain and discuss on the next email.

Ray
diff mbox

Patch

diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 0a5898b..d4e2d04 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -58,6 +58,36 @@ 
 
 	/include/ "bcm-cygnus-clock.dtsi"
 
+	core {
+		compatible = "simple-bus";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		timer@19020200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0x19020200 0x100>;
+			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&periph_clk>;
+		};
+
+		gic: interrupt-controller@19021000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x19021000 0x1000>,
+			      <0x19020100 0x100>;
+		};
+
+		L2: l2-cache {
+			compatible = "arm,pl310-cache";
+			reg = <0x19022000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+		};
+	};
+
 	pinctrl: pinctrl@0x0301d0c8 {
 		compatible = "brcm,cygnus-pinmux";
 		reg = <0x0301d0c8 0x30>,
@@ -225,28 +255,4 @@ 
 
 		brcm,nand-has-wp;
 	};
-
-	gic: interrupt-controller@19021000 {
-		compatible = "arm,cortex-a9-gic";
-		#interrupt-cells = <3>;
-		#address-cells = <0>;
-		interrupt-controller;
-		reg = <0x19021000 0x1000>,
-		      <0x19020100 0x100>;
-	};
-
-	L2: l2-cache {
-		compatible = "arm,pl310-cache";
-		reg = <0x19022000 0x1000>;
-		cache-unified;
-		cache-level = <2>;
-	};
-
-	timer@19020200 {
-		compatible = "arm,cortex-a9-global-timer";
-		reg = <0x19020200 0x100>;
-		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&periph_clk>;
-	};
-
 };