From patchwork Thu Sep 24 22:31:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 7261471 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 15F80BEEC1 for ; Thu, 24 Sep 2015 22:37:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2AB9A20925 for ; Thu, 24 Sep 2015 22:37:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 43701207E7 for ; Thu, 24 Sep 2015 22:37:39 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfF7R-0004FP-1j; Thu, 24 Sep 2015 22:36:01 +0000 Received: from mail-pa0-f47.google.com ([209.85.220.47]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfF4d-0007OL-5A for linux-arm-kernel@lists.infradead.org; Thu, 24 Sep 2015 22:33:09 +0000 Received: by pacex6 with SMTP id ex6so85034091pac.0 for ; Thu, 24 Sep 2015 15:32:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WXnbSYSInQ1ZCrVbiZ04Aa6oVzXxGX3sOSWlRMcaBJw=; b=X3uc6A7X3YWe9xQyabj0SrPXouw9R7Dsh4diUj/K6uE93O+60HsxEIBehfWVoz/0UH NYgvkNap859MSv2q0F/I9k0HSVrBAT7cWuNR3Wr/ZJ6mMW94gfFJU8zrVEBdl/EweyZm +7lsfq09okAYvdBr2Xvh5zWQKubESTsrvdFJxNPmRyDzUyqBTApHBblRHdKhJ7mfaBfp CX9pJ8LaYJACflbdyORbsO1bYNANevKL5fI9wtSeH0BMv2mcR0gNB0LfTfQmdUctu+5+ bWEgr6vDjhmy3eV+/GZNzXnxNvLMoubXvXGk7jhwX7o0pKiPv/tzv4XEeeP9u1Uq2VCO +zeA== X-Gm-Message-State: ALoCoQnQo9IXPamR2+RxPDAKhCTfs/CnEdknziveV/bQD8S2g+yfTlGnb25KDn6QgBWZ9DShWuxQ X-Received: by 10.66.236.129 with SMTP id uu1mr2657904pac.34.1443133966497; Thu, 24 Sep 2015 15:32:46 -0700 (PDT) Received: from localhost.localdomain ([40.139.248.3]) by smtp.gmail.com with ESMTPSA id ll9sm325723pbc.42.2015.09.24.15.32.41 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Sep 2015 15:32:45 -0700 (PDT) From: Shannon Zhao To: kvmarm@lists.cs.columbia.edu Subject: [PATCH v3 12/20] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Date: Thu, 24 Sep 2015 15:31:17 -0700 Message-Id: <1443133885-3366-13-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> References: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150924_153307_663314_DE26B069 X-CRM114-Status: GOOD ( 13.27 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, peter.huangpeng@huawei.com, linux-arm-kernel@lists.infradead.org, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 34 ++++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 98da5a2..e52325c 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -519,6 +519,18 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; break; } + case PMINTENSET_EL1: { + val = *vcpu_reg(vcpu, p->Rt); + vcpu_sys_reg(vcpu, r->reg) |= val; + vcpu_sys_reg(vcpu, PMINTENCLR_EL1) |= val; + break; + } + case PMINTENCLR_EL1: { + val = *vcpu_reg(vcpu, p->Rt); + vcpu_sys_reg(vcpu, r->reg) &= ~val; + vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; + break; + } case PMCR_EL0: { /* Only update writeable bits of PMCR */ val = vcpu_sys_reg(vcpu, r->reg); @@ -708,10 +720,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* PMINTENSET_EL1 */ { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMINTENSET_EL1 }, /* PMINTENCLR_EL1 */ { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMINTENCLR_EL1 }, /* MAIR_EL1 */ { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000), @@ -1022,6 +1034,18 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, vcpu_cp15(vcpu, c9_PMCNTENSET) &= ~val; break; } + case c9_PMINTENSET: { + val = *vcpu_reg(vcpu, p->Rt); + vcpu_cp15(vcpu, r->reg) |= val; + vcpu_cp15(vcpu, c9_PMINTENCLR) |= val; + break; + } + case c9_PMINTENCLR: { + val = *vcpu_reg(vcpu, p->Rt); + vcpu_cp15(vcpu, r->reg) &= ~val; + vcpu_cp15(vcpu, c9_PMINTENSET) &= ~val; + break; + } case c9_PMCR: { /* Only update writeable bits of PMCR */ val = vcpu_cp15(vcpu, r->reg); @@ -1108,8 +1132,10 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_cp15_regs, reset_unknown_cp15, c9_PMXEVCNTR }, { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi }, - { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi }, - { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMINTENSET }, + { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMINTENCLR }, { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },