From patchwork Fri Sep 25 02:14:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 7262051 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 732E3BEEC1 for ; Fri, 25 Sep 2015 02:17:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AAB1B20B17 for ; Fri, 25 Sep 2015 02:17:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CBBDB20B16 for ; Fri, 25 Sep 2015 02:17:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfIYF-0000g7-Be; Fri, 25 Sep 2015 02:15:55 +0000 Received: from mail-pa0-f43.google.com ([209.85.220.43]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfIY5-0000Td-8Q; Fri, 25 Sep 2015 02:15:46 +0000 Received: by pacex6 with SMTP id ex6so90197725pac.0; Thu, 24 Sep 2015 19:15:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4sTZOa0bxTz/AGHIsNrnlzMxLEqeMb1spqGu9COE9L0=; b=TMAFLWu1RB8fWDFowS2EX4dc4Qy+SxNXjzbkwp9ijQrs8wOmYLVzMZYetA9D4WU5AG mtlpkD0Ey6BmCdv9yF/eAmN4kw7cIqSXnIlBJuRCxA8Zih4JHR5NjG8dAS1Xa4v94DBq FASTzXhqKjIZca1vlswwgcLli5rd2MjzPH9RWt5tnbTSSpTWKYAvmc93Xs+mQL3yeUA1 XYrOq9QOzca3EmonhmWVC5jMb6pwTcnXrD83G5ZMSMiXkIYO4RQZX8u97r6RMVsuZkUl kYgSHKb2I7vEGVVYdzhpPaUOpE43V5rSjrkdgMTmVU/84UzLgEduOF91+mizUxCjUJdr DPaw== X-Received: by 10.68.195.3 with SMTP id ia3mr3710037pbc.106.1443147324705; Thu, 24 Sep 2015 19:15:24 -0700 (PDT) Received: from localhost.localdomain ([103.47.144.164]) by smtp.gmail.com with ESMTPSA id bk8sm876722pad.18.2015.09.24.19.15.19 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Sep 2015 19:15:23 -0700 (PDT) From: Caesar Wang To: heiko@sntech.de, daniel.lezcano@linaro.org, will.deacon@arm.com, catalin.marinas@arm.com Subject: [PATCH v2 1/4] clocksource: rockchip: Make the driver more compatible Date: Fri, 25 Sep 2015 10:14:55 +0800 Message-Id: <1443147298-12603-2-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1443147298-12603-1-git-send-email-wxt@rock-chips.com> References: <1443147298-12603-1-git-send-email-wxt@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150924_191545_505881_C5E38302 X-CRM114-Status: GOOD ( 11.44 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Caesar Wang , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Build the arm64 SoCs (e.g.: RK3368) on Rockchip platform, There are some failure with build up on timer driver for rockchip. Says: /tmp/ccdAnNy5.s:47: Error: missing immediate expression at operand 1 -- `dsb` ... The problem was different semantics of dsb on btw arm32 and arm64, Here we can convert the dsb with insteading of dsb(sy).The "sy" param is the default which you are allow to omit, so on arm32 dsb()and dsb(sy) are the same. Signed-off-by: Caesar Wang Acked-by: Daniel Lezcano Tested-by: Caesar Wang --- Changes in v2: - As Heiko/Daniel comments, let's split it into two patch. Changes in v1: - As Russell, Thomas, Daniel comments, let's replace NO_IRQ by '!irq'. drivers/clocksource/rockchip_timer.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c index bb2c2b0..3ace7ac 100644 --- a/drivers/clocksource/rockchip_timer.c +++ b/drivers/clocksource/rockchip_timer.c @@ -49,14 +49,14 @@ static inline void __iomem *rk_base(struct clock_event_device *ce) static inline void rk_timer_disable(struct clock_event_device *ce) { writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG); - dsb(); + dsb(sy); } static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags) { writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags, rk_base(ce) + TIMER_CONTROL_REG); - dsb(); + dsb(sy); } static void rk_timer_update_counter(unsigned long cycles, @@ -64,13 +64,13 @@ static void rk_timer_update_counter(unsigned long cycles, { writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0); writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1); - dsb(); + dsb(sy); } static void rk_timer_interrupt_clear(struct clock_event_device *ce) { writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS); - dsb(); + dsb(sy); } static inline int rk_timer_set_next_event(unsigned long cycles,