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Tue, 29 Sep 2015 10:44:35 +0800 (CST) From: Xing Zheng To: heiko@sntech.de Subject: [PATCH v3 8/8] rockchip: make sure timer5 is enabled on rk3036 platforms Date: Tue, 29 Sep 2015 10:44:31 +0800 Message-Id: <1443494671-16035-1-git-send-email-zhengxing@rock-chips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1443492833-15630-1-git-send-email-zhengxing@rock-chips.com> References: <1443492833-15630-1-git-send-email-zhengxing@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150928_225027_712986_8130043B X-CRM114-Status: GOOD ( 12.54 ) X-Spam-Score: -0.2 (/) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, zhengxing@rock-chips.com, linux@arm.linux.org.uk, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY, URIBL_BLACK autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The timer5 supplies the architected timer and thus as has to run when the system clocksource and clockevents drivers are registered. --- Changes in v3: Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner arch/arm/mach-rockchip/rockchip.c | 44 +++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index b6cf3b4..d483b71 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -29,31 +29,38 @@ #include "core.h" #include "pm.h" +#define RK3036_TIMER_PHYS 0x20044000 + #define RK3288_GRF_SOC_CON0 0x244 #define RK3288_TIMER6_7_PHYS 0xff810000 +static void rockchip_init_arch_timer_supply(resource_size_t phys, int offs) +{ + void __iomem *reg_base = ioremap(phys, SZ_16K); + + /* + * Most/all uboot versions for Rockchip SoCs don't enable + * timer which is needed for the architected timer to work. + * So make sure it is running during early boot. + */ + if (reg_base) { + writel(0, reg_base + offs + 0x10); + writel(0xffffffff, reg_base + offs); + writel(0xffffffff, reg_base + offs + 0x04); + writel(1, reg_base + offs + 0x10); + dsb(); + iounmap(reg_base); + } else { + pr_err("rockchip: could not map timer registers\n"); + } +} + static void __init rockchip_timer_init(void) { if (of_machine_is_compatible("rockchip,rk3288")) { struct regmap *grf; - void __iomem *reg_base; - /* - * Most/all uboot versions for rk3288 don't enable timer7 - * which is needed for the architected timer to work. - * So make sure it is running during early boot. - */ - reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); - if (reg_base) { - writel(0, reg_base + 0x30); - writel(0xffffffff, reg_base + 0x20); - writel(0xffffffff, reg_base + 0x24); - writel(1, reg_base + 0x30); - dsb(); - iounmap(reg_base); - } else { - pr_err("rockchip: could not map timer7 registers\n"); - } + rockchip_init_arch_timer_supply(RK3288_TIMER6_7_PHYS, 0x20); /* * Disable auto jtag/sdmmc switching that causes issues @@ -64,6 +71,8 @@ static void __init rockchip_timer_init(void) regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000); else pr_err("rockchip: could not get grf syscon\n"); + } else if (of_machine_is_compatible("rockchip,rk3036")) { + rockchip_init_arch_timer_supply(RK3036_TIMER_PHYS, 0xa0); } of_clk_init(NULL); @@ -79,6 +88,7 @@ static void __init rockchip_dt_init(void) static const char * const rockchip_board_dt_compat[] = { "rockchip,rk2928", + "rockchip,rk3036", "rockchip,rk3066a", "rockchip,rk3066b", "rockchip,rk3188",