From patchwork Fri Oct 2 17:56:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 7318211 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 27DA6BEEA4 for ; Fri, 2 Oct 2015 17:59:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3AA2E2081C for ; Fri, 2 Oct 2015 17:59:39 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 64D182081B for ; Fri, 2 Oct 2015 17:59:38 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zi4aP-0007aS-Ea; Fri, 02 Oct 2015 17:57:37 +0000 Received: from mail-gw3-out.broadcom.com ([216.31.210.64]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zi4aD-00071s-Jg; Fri, 02 Oct 2015 17:57:26 +0000 X-IronPort-AV: E=Sophos;i="5.17,624,1437462000"; d="scan'208";a="76471608" Received: from irvexchcas08.broadcom.com (HELO IRVEXCHCAS08.corp.ad.broadcom.com) ([10.9.208.57]) by mail-gw3-out.broadcom.com with ESMTP; 02 Oct 2015 11:23:04 -0700 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.3.235.1; Fri, 2 Oct 2015 10:57:25 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.3.235.1; Fri, 2 Oct 2015 10:57:24 -0700 Received: from anup-HP-Compaq-8100-Elite-CMT-PC.ban.broadcom.com (unknown [10.131.91.107]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 41A8B40FE5; Fri, 2 Oct 2015 10:54:31 -0700 (PDT) From: Anup Patel To: Subject: [PATCH 3/5] mtd: brcmnand: Optional DT flag to reset IPROC NAND controller Date: Fri, 2 Oct 2015 23:26:44 +0530 Message-ID: <1443808606-21203-4-git-send-email-anup.patel@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1443808606-21203-1-git-send-email-anup.patel@broadcom.com> References: <1443808606-21203-1-git-send-email-anup.patel@broadcom.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151002_105725_907310_D73DDC7B X-CRM114-Status: GOOD ( 12.85 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Florian Fainelli , Scott Branden , Pawel Moll , Ian Campbell , Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, Ray Jui , Vikram Prakash , Rob Herring , linux-mtd@lists.infradead.org, Sandeep Tripathy , Kumar Gala , Pramod KUMAR , bcm-kernel-feedback-list@broadcom.com, Brian Norris , David Woodhouse , Anup Patel Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The BRCM NAND controller on NS2 SoC requires a reset to cleanup previously configured NAND controller state. This patch adds optional boolean device tree flag named "brcm,nand-iproc-reset". If this flag is present in NAND controller DT node then BRCM IPROC NAND driver will reset the NAND controller before any commands are issued. Signed-off-by: Anup Patel Reviewed-by: Pramod KUMAR Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- drivers/mtd/nand/brcmnand/iproc_nand.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mtd/nand/brcmnand/iproc_nand.c b/drivers/mtd/nand/brcmnand/iproc_nand.c index 683495c..d837207 100644 --- a/drivers/mtd/nand/brcmnand/iproc_nand.c +++ b/drivers/mtd/nand/brcmnand/iproc_nand.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -35,6 +36,10 @@ struct iproc_nand_soc_priv { #define IPROC_NAND_APB_LE_MODE BIT(24) #define IPROC_NAND_INT_CTRL_READ_ENABLE BIT(6) +#define IPROC_NAND_RESET_OFFSET 0x3f8 +#define IPROC_NAND_RESET_BIT_SHIFT 0 +#define IPROC_NAND_RESET_BIT BIT(IPROC_NAND_RESET_BIT_SHIFT) + static bool iproc_nand_intc_ack(struct brcmnand_soc *soc) { struct iproc_nand_soc_priv *priv = soc->priv; @@ -93,6 +98,7 @@ static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare) static int iproc_nand_probe(struct platform_device *pdev) { + u32 reset; struct device *dev = &pdev->dev; struct iproc_nand_soc_priv *priv; struct brcmnand_soc *soc; @@ -124,6 +130,19 @@ static int iproc_nand_probe(struct platform_device *pdev) soc->ctlrdy_set_enabled = iproc_nand_intc_set; soc->prepare_data_bus = iproc_nand_apb_access; + if (of_property_read_bool(dev->of_node, "brcm,nand-iproc-reset")) { + /* Put controller in reset and wait 10 usecs */ + reset = readl(priv->idm_base + IPROC_NAND_RESET_OFFSET); + reset |= IPROC_NAND_RESET_BIT; + writel(reset, priv->idm_base + IPROC_NAND_RESET_OFFSET); + udelay(10); + /* Bring controller out of reset and wait 10 usecs */ + reset = readl(priv->idm_base + IPROC_NAND_RESET_OFFSET); + reset &= ~IPROC_NAND_RESET_BIT; + writel(reset, priv->idm_base + IPROC_NAND_RESET_OFFSET); + udelay(10); + } + return brcmnand_probe(pdev, soc); }