From patchwork Tue Oct 6 01:22:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcin Wojtas X-Patchwork-Id: 7332891 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 78021BF90C for ; Tue, 6 Oct 2015 01:18:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9872420693 for ; Tue, 6 Oct 2015 01:18:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC7B62068E for ; Tue, 6 Oct 2015 01:18:51 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZjGrf-0003fC-Nn; Tue, 06 Oct 2015 01:16:23 +0000 Received: from mail-la0-f54.google.com ([209.85.215.54]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZjGrY-0003aM-Kc for linux-arm-kernel@lists.infradead.org; Tue, 06 Oct 2015 01:16:17 +0000 Received: by labzv5 with SMTP id zv5so135361068lab.1 for ; Mon, 05 Oct 2015 18:15:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tHXocJza6JlbPA7QCWR4F4gbHGv5ejjauxttqwKH58M=; b=ZKF2vny52Z//cvXXyPA207WYAg47nXyZwRD3onHo4tMlejU3QQdBONv6es25F/jJd7 OXJnrkWgrFr6gsN9bFWNAu60VPfjVQHtNKJQZLhbRk9Tfn6FoglCZzU1CdiIXu16Wb37 55k84rRE6CLIiEqibjEzmlQpDg+TNeO+MzUe8FTuE0OH36xcsLbyn7o0w/uZDgowDFce z0i9B+hyRE29W1VzuGrR+JBWl1D73KpPRI0MvnZL+mFP4Ig+nZTBKbOq+i8iZ6k9JLtN VVnEon/l1IWEJFZqDQCPYDb1voRvZ2xdyAgcTXJsHhLDlxV7NSLVMSSbsCX8Xgizyi6R I0OQ== X-Gm-Message-State: ALoCoQk0tosQR/Hbn3Uj7DoPDiBglDiha0J4BEM2LF/OF9prYK95k+8jBPHMPU6d78F1EdCUD6aC X-Received: by 10.112.184.137 with SMTP id eu9mr13048720lbc.21.1444094154578; Mon, 05 Oct 2015 18:15:54 -0700 (PDT) Received: from enkidu.semihalf.local (cardhu.semihalf.com. [213.17.239.108]) by smtp.gmail.com with ESMTPSA id x1sm4694780lbb.32.2015.10.05.18.15.52 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Oct 2015 18:15:53 -0700 (PDT) From: Marcin Wojtas To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org Subject: [PATCH 2/8] mmc: sdhci-pxav3: disable clock inversion for HS MMC cards Date: Tue, 6 Oct 2015 03:22:36 +0200 Message-Id: <1444094562-31165-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1444094562-31165-1-git-send-email-mw@semihalf.com> References: <1444094562-31165-1-git-send-email-mw@semihalf.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151005_181616_992327_744F34F2 X-CRM114-Status: GOOD ( 11.78 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thomas.petazzoni@free-electrons.com, andrew@lunn.ch, ulf.hansson@linaro.org, jason@lakedaemon.net, tawfik@marvell.com, jaz@semihalf.com, stable@vger.kernel.org, nadavh@marvell.com, alior@marvell.com, gregory.clement@free-electrons.com, mw@semihalf.com, sebastian.hesselbarth@gmail.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Nadav Haklai According to 'FE-2946959' erratum the clock inversion option is needed to support slow frequencies when the card input hold time requirement is high. This setting is not required for high speed MMC and might cause timing violation. Signed-off-by: Nadav Haklai Cc: # v4.2 Reviewed-by: Gregory CLEMENT --- drivers/mmc/host/sdhci-pxav3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index 976cddd..89a9e49 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -291,6 +291,9 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) uhs == MMC_TIMING_UHS_DDR50) { reg_val &= ~SDIO3_CONF_CLK_INV; reg_val |= SDIO3_CONF_SD_FB_CLK; + } else if (uhs == MMC_TIMING_MMC_HS) { + reg_val &= ~SDIO3_CONF_CLK_INV; + reg_val &= ~SDIO3_CONF_SD_FB_CLK; } else { reg_val |= SDIO3_CONF_CLK_INV; reg_val &= ~SDIO3_CONF_SD_FB_CLK;