From patchwork Sun Oct 18 18:24:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 7431791 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7AC6CBEEA4 for ; Sun, 18 Oct 2015 18:29:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 95D0C2058A for ; Sun, 18 Oct 2015 18:29:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC30220571 for ; Sun, 18 Oct 2015 18:29:06 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZnsgD-0006Sq-Hx; Sun, 18 Oct 2015 18:27:37 +0000 Received: from mail-pa0-f46.google.com ([209.85.220.46]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Znsek-0004mM-8n for linux-arm-kernel@lists.infradead.org; Sun, 18 Oct 2015 18:26:06 +0000 Received: by pabrc13 with SMTP id rc13so167566488pab.0 for ; Sun, 18 Oct 2015 11:25:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z4+k4jGafHgm/DZ42xzifcgcTz/1okSQ3FxPrMtzcy8=; b=JEPH47tiiU34Wbco3eHO+FL4xjPfWQFJz4DK7B4zs8PPEnm0hJFPThxyB8/KNJVHqW 3UCRwLwXARLDydrB9LijiY7xOfC1IOuPghjjeo+oz2KMy/omMn4+mC/mt95ldpyiecxg bz5Wm7E/NnhNm7fj9JsH9XgHR65WfIwepFxo97K4uxPQGGwX38h13do8fLa3mvLj2Hb6 R7TO2MGqI0I4Sl7BcwvMuDcT1VYUOaiE7+csccjJGKfOyTP86254urJ3YHb0W1+MlJZK uS6k8k/rHGW4PwCc8qRFGW4pkIPmYf1boCJrQhjXF1yuVZPvb1LGp52Uvu+S3CsNeXaY liUg== X-Gm-Message-State: ALoCoQky2jPutLE0zg7DXlXtuw5QNs5K0H0/kNIBwqJgWUTN0nU7MVF3wx8pDwAoalSuja9mu4ab X-Received: by 10.68.184.5 with SMTP id eq5mr30034740pbc.130.1445192745528; Sun, 18 Oct 2015 11:25:45 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [184.64.168.246]) by smtp.gmail.com with ESMTPSA id hq1sm20402076pbb.43.2015.10.18.11.25.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Oct 2015 11:25:45 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net, nicolas.pitre@linaro.org Subject: [PATCH V2 10/30] coresight: etm3x: consolidating initial config Date: Sun, 18 Oct 2015 12:24:27 -0600 Message-Id: <1445192687-24112-11-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1445192687-24112-1-git-send-email-mathieu.poirier@linaro.org> References: <1445192687-24112-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151018_112606_384127_538E6899 X-CRM114-Status: GOOD ( 12.76 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, mathieu.poirier@linaro.org, pawel.moll@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, adrian.hunter@intel.com, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There is really no point having two functions to take care of doing the initials tracer configuration. As such moving everything to 'etm_set_default()'. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm3x.c | 37 ++++++++++----------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 8bd161584f85..cc0b08437419 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -41,7 +41,6 @@ module_param_named(boot_enable, boot_enable, int, S_IRUGO); /* The number of ETM/PTM currently registered */ static int etm_count; static struct etm_drvdata *etmdrvdata[NR_CPUS]; -static void etm_init_default_data(struct etm_config *config); /* * Memory mapped writes to clear os lock are not supported on some processors @@ -199,7 +198,7 @@ struct etm_config *get_etm_config(struct etm_drvdata *drvdata) return NULL; /* Set default config */ - etm_init_default_data(config); + etm_set_default(config); drvdata->config = config; out: return drvdata->config; @@ -212,6 +211,19 @@ void etm_set_default(struct etm_config *config) if (WARN_ON_ONCE(!config)) return; + /* + * Taken verbatim from the TRM: + * + * To trace all memory: + * set bit [24] in register 0x009, the ETMTECR1, to 1 + * set all other bits in register 0x009, the ETMTECR1, to 0 + * set all bits in register 0x007, the ETMTECR2, to 0 + * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). + */ + config->enable_ctrl1 = BIT(24); + config->enable_ctrl2 = 0x0; + config->enable_event = ETM_HARD_WIRE_RES_A; + config->trigger_event = ETM_DEFAULT_EVENT_VAL; config->enable_event = ETM_HARD_WIRE_RES_A; @@ -565,27 +577,6 @@ static void etm_init_arch_data(void *info) CS_LOCK(drvdata->base); } -static void etm_init_default_data(struct etm_config *config) -{ - if (WARN_ON_ONCE(!config)) - return; - - etm_set_default(config); - - /* - * Taken verbatim from the TRM: - * - * To trace all memory: - * set bit [24] in register 0x009, the ETMTECR1, to 1 - * set all other bits in register 0x009, the ETMTECR1, to 0 - * set all bits in register 0x007, the ETMTECR2, to 0 - * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). - */ - config->enable_ctrl1 = BIT(24); - config->enable_ctrl2 = 0x0; - config->enable_event = ETM_HARD_WIRE_RES_A; -} - static void etm_init_trace_id(struct etm_drvdata *drvdata) { /*