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[184.64.168.246]) by smtp.gmail.com with ESMTPSA id hq1sm20402076pbb.43.2015.10.18.11.25.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Oct 2015 11:25:56 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net, nicolas.pitre@linaro.org Subject: [PATCH V2 14/30] coresight: etm3x: implementing perf_start/stop() API Date: Sun, 18 Oct 2015 12:24:31 -0600 Message-Id: <1445192687-24112-15-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1445192687-24112-1-git-send-email-mathieu.poirier@linaro.org> References: <1445192687-24112-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151018_192619_078781_5651C572 X-CRM114-Status: GOOD ( 14.94 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, mathieu.poirier@linaro.org, pawel.moll@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, adrian.hunter@intel.com, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adding an API to deal with runtime PM (and anything else) that might be required by a tracer before and after it is to be used by the Perf framework. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm3x.c | 12 ++++++++++++ include/linux/coresight.h | 5 +++++ 2 files changed, 17 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index f565554744fe..9b4c0359ca29 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -459,6 +459,16 @@ static int etm_trace_id(struct coresight_device *csdev) return etm_get_trace_id(drvdata); } +static int perf_etm_start(struct coresight_device *csdev) +{ + return pm_runtime_get_sync(csdev->dev.parent); +} + +static int perf_etm_stop(struct coresight_device *csdev) +{ + return pm_runtime_put(csdev->dev.parent); +} + static void *perf_etm_get_config(struct coresight_device *csdev, struct perf_event *event) { @@ -625,6 +635,8 @@ static void sysfs_etm_disable(struct coresight_device *csdev) static const struct coresight_ops_source etm_source_ops = { .cpu_id = etm_cpu_id, .trace_id = etm_trace_id, + .perf_start = perf_etm_start, + .perf_stop = perf_etm_stop, .perf_get_config = perf_etm_get_config, .perf_set_config = perf_etm_set_config, .perf_enable = perf_etm_enable, diff --git a/include/linux/coresight.h b/include/linux/coresight.h index b853d722346b..0601da01eeb2 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -209,6 +209,9 @@ struct coresight_ops_link { * is associated to. * @trace_id: returns the value of the component's trace ID as known to the HW. + * @perf_start: operations to be done before a tracer can be used. + * @perf_stop: operations to be done when a tracer is + * no longer needed. * @perf_get_config: builds the ETM configuration after event' specifics. * @perf_set_config: associate a tracer with a configuration.. * @perf_enable: enables tracing for a source, from Perf. @@ -219,6 +222,8 @@ struct coresight_ops_link { struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); int (*trace_id)(struct coresight_device *csdev); + int (*perf_start)(struct coresight_device *csdev); + int (*perf_stop)(struct coresight_device *csdev); void *(*perf_get_config)(struct coresight_device *csdev, struct perf_event *event); void (*perf_set_config)(struct coresight_device *csdev, void *config);