From patchwork Sun Oct 18 18:24:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 7431881 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E1FDFBEEA4 for ; Sun, 18 Oct 2015 18:30:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EAA462053D for ; Sun, 18 Oct 2015 18:30:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9422020524 for ; Sun, 18 Oct 2015 18:30:55 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Znshr-0000nF-4K; Sun, 18 Oct 2015 18:29:19 +0000 Received: from mail-pa0-f50.google.com ([209.85.220.50]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Znsf5-0004uo-NN for linux-arm-kernel@lists.infradead.org; Sun, 18 Oct 2015 18:26:29 +0000 Received: by padhk11 with SMTP id hk11so6282835pad.1 for ; Sun, 18 Oct 2015 11:26:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AEaBsnDBR7OR5PaIq1LoL7GVrU1h2QdfvK+eJeuw6kA=; b=YfnR6mpUNqHysuBSLOg8PkfI/+OcQyRseurUpVqke2ST2sAZYIOsBwfjJShfKRB9EU yVvgjzTd0s4WuIRqOMYwDxKunvMivYeGda+JuF9D4NTsPyrlg7LgRita/iWPUeFUheEG DGlOjESuhUV6LMR+SMZ7k5mfOm4PWau5A7oBpxwGdCYc5uz5tqfUSJtjhMIWIL/lt0Fi /9hbhn1k5lZ4kAxXlRNnIjHvzES+CD8MAHQ5TOoOfjB6In5M4mvhtwkpyqYMQtWqFKqV 9ll4+Hkf1BmOfdLcMxNqss1tFNTyzKbv+UWtCp/2wsV1dm8UpqqEjbK3CS1H4/4wcokq 409w== X-Gm-Message-State: ALoCoQlFuuyqXFL1SByGJDNAYSt08naZmrLGZJblLaGJ9g2lZUBIOXyNH5ZLCJWWsFfzg+WT91jg X-Received: by 10.68.161.162 with SMTP id xt2mr29630499pbb.89.1445192766893; Sun, 18 Oct 2015 11:26:06 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [184.64.168.246]) by smtp.gmail.com with ESMTPSA id hq1sm20402076pbb.43.2015.10.18.11.26.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 18 Oct 2015 11:26:06 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net, nicolas.pitre@linaro.org Subject: [PATCH V2 20/30] coresight: etb10: implementing buffer set/reset() API Date: Sun, 18 Oct 2015 12:24:37 -0600 Message-Id: <1445192687-24112-21-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1445192687-24112-1-git-send-email-mathieu.poirier@linaro.org> References: <1445192687-24112-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151018_112627_817967_FF8A4CAD X-CRM114-Status: GOOD ( 17.97 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, mathieu.poirier@linaro.org, pawel.moll@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, adrian.hunter@intel.com, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Implementing perf related APIs to activate and terminate a trace session. More specifically dealing with the sink buffer's internal mechanic along with perf's API to start and stop interactions with the ring buffers. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 58 +++++++++++++++++++++++++++ include/linux/coresight.h | 9 +++++ 2 files changed, 67 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 7f34e7af465e..ca2c4b42464d 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -28,6 +28,7 @@ #include #include #include +#include #include @@ -306,10 +307,67 @@ static void *etb_setup_aux(struct coresight_device *csdev, int cpu, return buf; } +static int etb_set_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config) +{ + int ret = 0; + unsigned long head; + struct cs_buffers *buf = sink_config; + struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + /* This sink can only be used by a single session */ + if (local_xchg(&drvdata->in_use, 1)) + return -EBUSY; + + /* how much space do we have in this session */ + buf->size = handle->size; + + /* wrap head around to the amount of space we have */ + head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1); + + /* find the page to write to */ + buf->cur = head / PAGE_SIZE; + + /* and offset within that page */ + buf->offset = head % PAGE_SIZE; + + local_set(&buf->head, head); + local_set(&buf->data_size, 0); + + return ret; +} + +static void etb_reset_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config) +{ + struct cs_buffers *buf = sink_config; + struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + if (buf) { + /* + * In snapshot mode ->data_size holds the new address of the + * ring buffer's head. The size itself is the whole address + * range since we want the latest information. + */ + if (buf->snapshot) + handle->head = local_xchg(&buf->data_size, + buf->nr_pages << PAGE_SHIFT); + + perf_aux_output_end(handle, local_xchg(&buf->data_size, 0), + local_xchg(&buf->lost, 0)); + } + + local_set(&drvdata->in_use, 0); +} + static const struct coresight_ops_sink etb_sink_ops = { .enable = etb_enable, .disable = etb_disable, .setup_aux = etb_setup_aux, + .set_buffer = etb_set_buffer, + .reset_buffer = etb_reset_buffer, }; static const struct coresight_ops etb_cs_ops = { diff --git a/include/linux/coresight.h b/include/linux/coresight.h index b1c25eba83b4..78202d5ea58a 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -15,6 +15,7 @@ #include #include +#include /* Peripheral id registers (0xFD0-0xFEC) */ #define CORESIGHT_PERIPHIDR4 0xfd0 @@ -188,12 +189,20 @@ struct coresight_device { * @enable: enables the sink. * @disable: disables the sink. * @setup_aux: initialises perf's ring buffer for trace collection. + * @set_buffer: initialises buffer mechanic before a trace session. + * @reset_buffer: finalises buffer mechanic after a trace session. */ struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev); void (*disable)(struct coresight_device *csdev); void *(*setup_aux)(struct coresight_device *csdev, int cpu, void **pages, int nr_pages, bool overwrite); + int (*set_buffer)(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config); + void (*reset_buffer)(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config); }; /**