From patchwork Mon Oct 19 08:08:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 7434051 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 069FCBEEA4 for ; Mon, 19 Oct 2015 08:11:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0E8C3206F0 for ; Mon, 19 Oct 2015 08:11:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4B1DA206DF for ; Mon, 19 Oct 2015 08:11:18 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zo5Vk-0000nz-KW; Mon, 19 Oct 2015 08:09:40 +0000 Received: from down.free-electrons.com ([37.187.137.238] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zo5VS-0000gT-N4 for linux-arm-kernel@lists.infradead.org; Mon, 19 Oct 2015 08:09:23 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id 20AD41F0A; Mon, 19 Oct 2015 10:09:04 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (AToulouse-657-1-1073-161.w92-134.abo.wanadoo.fr [92.134.79.161]) by mail.free-electrons.com (Postfix) with ESMTPSA id DF58DA34; Mon, 19 Oct 2015 10:09:03 +0200 (CEST) From: Maxime Ripard To: Mike Turquette , Stephen Boyd , Emilio Lopez Subject: [PATCH v5 3/5] clk: sunxi: pll2: Add A13 support Date: Mon, 19 Oct 2015 10:08:57 +0200 Message-Id: <1445242139-20965-4-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.5.3 In-Reply-To: <1445242139-20965-1-git-send-email-maxime.ripard@free-electrons.com> References: <1445242139-20965-1-git-send-email-maxime.ripard@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151019_010923_164481_83F30126 X-CRM114-Status: GOOD ( 12.45 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-sunxi@googlegroups.com, Hans de Goede , Chen-Yu Tsai , Maxime Ripard , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The A13, unlike the A10 and A20, doesn't use a pass-through exception for the 0 value in the pre and post dividers, but increments all the values written in the register by one. Add an exception for both these cases to handle them nicely. Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai --- drivers/clk/sunxi/clk-a10-pll2.c | 38 +++++++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c index a57742a8576d..5484c31ec568 100644 --- a/drivers/clk/sunxi/clk-a10-pll2.c +++ b/drivers/clk/sunxi/clk-a10-pll2.c @@ -41,9 +41,15 @@ #define SUN4I_PLL2_OUTPUTS 4 +struct sun4i_pll2_data { + u32 post_div_offset; + u32 pre_div_flags; +}; + static DEFINE_SPINLOCK(sun4i_a10_pll2_lock); -static void __init sun4i_pll2_setup(struct device_node *node) +static void __init sun4i_pll2_setup(struct device_node *node, + struct sun4i_pll2_data *data) { const char *clk_name = node->name, *parent; struct clk **clks, *base_clk, *prediv_clk; @@ -70,8 +76,7 @@ static void __init sun4i_pll2_setup(struct device_node *node) parent, 0, reg, SUN4I_PLL2_PRE_DIV_SHIFT, SUN4I_PLL2_PRE_DIV_WIDTH, - CLK_DIVIDER_ONE_BASED | - CLK_DIVIDER_ALLOW_ZERO, + data->pre_div_flags, &sun4i_a10_pll2_lock); if (!prediv_clk) { pr_err("Couldn't register the prediv clock\n"); @@ -122,7 +127,7 @@ static void __init sun4i_pll2_setup(struct device_node *node) */ val = readl(reg); val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT); - val |= SUN4I_PLL2_POST_DIV_VALUE << SUN4I_PLL2_POST_DIV_SHIFT; + val |= (SUN4I_PLL2_POST_DIV_VALUE - data->post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT; writel(val, reg); of_property_read_string_index(node, "clock-output-names", @@ -185,4 +190,27 @@ err_free_data: err_unmap: iounmap(reg); } -CLK_OF_DECLARE(sun4i_pll2, "allwinner,sun4i-a10-pll2-clk", sun4i_pll2_setup); + +static struct sun4i_pll2_data sun4i_a10_pll2_data = { + .pre_div_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, +}; + +static void __init sun4i_a10_pll2_setup(struct device_node *node) +{ + sun4i_pll2_setup(node, &sun4i_a10_pll2_data); +} + +CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk", + sun4i_a10_pll2_setup); + +static struct sun4i_pll2_data sun5i_a13_pll2_data = { + .post_div_offset = 1, +}; + +static void __init sun5i_a13_pll2_setup(struct device_node *node) +{ + sun4i_pll2_setup(node, &sun5i_a13_pll2_data); +} + +CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk", + sun5i_a13_pll2_setup);