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[91.46.156.88]) by smtp.gmail.com with ESMTPSA id qr6sm22665501wic.13.2015.10.21.09.13.32 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Oct 2015 09:13:34 -0700 (PDT) From: Jens Kuske To: Maxime Ripard , Chen-Yu Tsai , Mike Turquette , Linus Walleij , Rob Herring , Philipp Zabel , =?UTF-8?q?Emilio=20L=C3=B3pez?= Subject: [PATCH 1/6] clk: sunxi: Let divs clocks read the base factor clock name from devicetree Date: Wed, 21 Oct 2015 18:13:22 +0200 Message-Id: <1445444007-4260-2-git-send-email-jenskuske@gmail.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1445444007-4260-1-git-send-email-jenskuske@gmail.com> References: <1445444007-4260-1-git-send-email-jenskuske@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151021_091356_574680_AE4A62A7 X-CRM114-Status: GOOD ( 18.62 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Vishnu Patekar , linux-kernel@vger.kernel.org, Hans de Goede , linux-sunxi@googlegroups.com, Jens Kuske , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, the sunxi clock driver gets the name for the base factor clock of divs clocks from the name field in factors_data. This prevents reusing of the factor clock for clocks with same properties, but different name. This commit makes the divs setup function try to get a name from clock-output-names in the devicetree. It also removes the name field where possible and merges the sun4i PLL5 and PLL6 clocks. Signed-off-by: Jens Kuske --- drivers/clk/sunxi/clk-sunxi.c | 39 ++++++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index 9c79af0c..7c4aee0 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -704,21 +704,12 @@ static const struct factors_data sun4i_pll5_data __initconst = { .enable = 31, .table = &sun4i_pll5_config, .getter = sun4i_get_pll5_factors, - .name = "pll5", -}; - -static const struct factors_data sun4i_pll6_data __initconst = { - .enable = 31, - .table = &sun4i_pll5_config, - .getter = sun4i_get_pll5_factors, - .name = "pll6", }; static const struct factors_data sun6i_a31_pll6_data __initconst = { .enable = 31, .table = &sun6i_a31_pll6_config, .getter = sun6i_a31_get_pll6_factors, - .name = "pll6x2", }; static const struct factors_data sun5i_a13_ahb_data __initconst = { @@ -902,6 +893,7 @@ struct gates_data { #define SUNXI_DIVS_MAX_QTY 4 #define SUNXI_DIVISOR_WIDTH 2 +#define SUNXI_DIVS_BASE_NAME_MAX_LEN 8 struct divs_data { const struct factors_data *factors; /* data for the factor clock */ @@ -941,7 +933,7 @@ static const struct divs_data pll5_divs_data __initconst = { }; static const struct divs_data pll6_divs_data __initconst = { - .factors = &sun4i_pll6_data, + .factors = &sun4i_pll5_data, .ndivs = 4, .div = { { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ @@ -983,6 +975,8 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, struct clk_gate *gate = NULL; struct clk_fixed_factor *fix_factor; struct clk_divider *divider; + struct factors_data factors = *data->factors; + char base_name[SUNXI_DIVS_BASE_NAME_MAX_LEN]; void __iomem *reg; int ndivs = SUNXI_DIVS_MAX_QTY, i = 0; int flags, clkflags; @@ -991,8 +985,31 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, if (data->ndivs) ndivs = data->ndivs; + /* Try to find a name for base factor clock */ + for (i = 0; i < ndivs; i++) { + if (data->div[i].self) { + of_property_read_string_index(node, "clock-output-names", + i, &factors.name); + break; + } + } + /* If we don't have a .self clk use the first output-name up to '_' */ + if (factors.name == NULL) { + of_property_read_string_index(node, "clock-output-names", + 0, &clk_name); + + for (i = 0; i < SUNXI_DIVS_BASE_NAME_MAX_LEN - 1 && + clk_name[i] != '_' && + clk_name[i] != '\0'; i++) { + base_name[i] = clk_name[i]; + } + + base_name[i] = '\0'; + factors.name = base_name; + } + /* Set up factor clock that we will be dividing */ - pclk = sunxi_factors_clk_setup(node, data->factors); + pclk = sunxi_factors_clk_setup(node, &factors); parent = __clk_get_name(pclk); reg = of_iomap(node, 0);