From patchwork Tue Nov 3 08:10:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 7540541 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0F59FBEEA4 for ; Tue, 3 Nov 2015 08:12:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 25EE520767 for ; Tue, 3 Nov 2015 08:12:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3A6C720763 for ; Tue, 3 Nov 2015 08:12:47 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZtWgQ-0005fc-CV; Tue, 03 Nov 2015 08:11:10 +0000 Received: from mail-pa0-f68.google.com ([209.85.220.68]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZtWgI-0005Te-1R; Tue, 03 Nov 2015 08:11:04 +0000 Received: by padfb7 with SMTP id fb7so1310395pad.0; Tue, 03 Nov 2015 00:10:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=TMBbeJcRNSeqgM1hGRwlfQC4i2AMlhP307kADqizpAI=; b=R8xLCeSJDA+HzICpWn1+N8GJB5HTIA7H49KdI/CGQnWlSWhwKEx4DypTxbxKAuZG+2 AcGbl48kRwdvVgzmSzJwT7ESp3EZ+VaoGhIaV1wjwNlbcs+IuV1B4eOZrd8CoeWUUOb6 Tzxf1fFEJpiYZf/Av4fIoJVYCx02BdsiYlmcfFfQ5Rjp8ej8poLHDm7hq+TfpuzwSHTF fWt2fySW1kUmZgDQWDksPInwzhzU+PY6VjYv70AvSf/Y/o4OdnqNjiHQUQ/Ddj/h6X+Z op+W2FqQ8tCx5BTfQC15h2qebCZk53cz8SrccJPZyP7rW2vqirBIlVQUzgB63d6CDkwZ dFjA== X-Received: by 10.68.174.34 with SMTP id bp2mr31944366pbc.102.1446538241067; Tue, 03 Nov 2015 00:10:41 -0800 (PST) Received: from localhost.localdomain ([103.46.142.37]) by smtp.gmail.com with ESMTPSA id uy1sm23053689pac.39.2015.11.03.00.10.32 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Nov 2015 00:10:40 -0800 (PST) From: Caesar Wang To: Russell King , Heiko Stuebner Subject: [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325 Date: Tue, 3 Nov 2015 16:10:09 +0800 Message-Id: <1446538209-13490-2-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1446538209-13490-1-git-send-email-wxt@rock-chips.com> References: <1446538209-13490-1-git-send-email-wxt@rock-chips.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151103_001102_416130_6E0A801E X-CRM114-Status: GOOD ( 13.16 ) X-Spam-Score: -2.4 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huang Tao , Thomas Petazzoni , hl@rock-chips.com, Ard Biesheuvel , linux-kernel@vger.kernel.org, sjg@chromium.org, Stephen Boyd , dianders@chromium.org, Kever Yang , Nadav Haklai , linux-rockchip@lists.infradead.org, cwz@rock-chips.com, Jonathan Stone , Gregory CLEMENT , linux-arm-kernel@lists.infradead.org, Caesar Wang Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Huang Tao On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of two conditional store instructions with opposite condition code and updating the same register, the system might enter a deadlock if the second conditional instruction is an UNPREDICTABLE STR or STM instruction. This workaround setting bit[12] of the Feature Register prevents the erratum. This bit disables an optimisation applied to a sequence of 2 instructions that use opposing condition codes. Signed-off-by: Huang Tao Signed-off-by: Kever Yang Signed-off-by: Caesar Wang --- arch/arm/Kconfig | 13 +++++++++++++ arch/arm/mm/proc-v7.S | 12 ++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 639411f..554b57a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1263,6 +1263,19 @@ config ARM_ERRATA_773022 loop buffer may deliver incorrect instructions. This workaround disables the loop buffer to avoid the erratum. +config ARM_ERRATA_818325 + bool "ARM errata: Execution of an UNPREDICTABLE STR or STM instruction might deadlock" + depends on CPU_V7 + help + This option enables the workaround for the 818325 Cortex-A12 + (r0p0..r0p1-00lac0-rc11) erratum. When a CPU executes a sequence of + two conditional store instructions with opposite condition code and + updating the same register, the system might enter a deadlock if the + second conditional instruction is an UNPREDICTABLE STR or STM + instruction. This workaround setting bit[12] of the Feature Register + prevents the erratum. This bit disables an optimisation applied to a + sequence of 2 instructions that use opposing condition codes. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index de2b246..2b338ec 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -439,6 +439,18 @@ __v7_setup_cont: teq r0, r10 beq __ca9_errata + /* Cortex-A12 Errata */ + ldr r10, =0x00000c0d @ Cortex-A12 primary part number + teq r0, r10 + bne 5f +#ifdef CONFIG_ARM_ERRATA_818325 + teq r6, #0x00 @ present in r0p0 + teqne r6, #0x01 @ present in r0p1-00lac0-rc11 + mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register + orreq r10, r10, #1 << 12 @ set bit #12 + mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register + isb +#endif /* Cortex-A15 Errata */ ldr r10, =0x00000c0f @ Cortex-A15 primary part number teq r0, r10