From patchwork Thu Nov 5 02:32:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 7556861 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DB4BCBEEA4 for ; Thu, 5 Nov 2015 02:38:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0811C2082C for ; Thu, 5 Nov 2015 02:38:26 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23A6C20823 for ; Thu, 5 Nov 2015 02:38:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZuAPg-0005tY-6x; Thu, 05 Nov 2015 02:36:32 +0000 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZuAPd-0005s1-AB for linux-arm-kernel@lists.infradead.org; Thu, 05 Nov 2015 02:36:29 +0000 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.15.0.59/8.15.0.59) with SMTP id tA52YmTF013634; Wed, 4 Nov 2015 18:35:58 -0800 Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 1xyx878134-7 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 04 Nov 2015 18:35:58 -0800 Received: from SC-EXCH04.marvell.com (10.93.176.84) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Wed, 4 Nov 2015 18:35:44 -0800 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server id 15.0.1044.25 via Frontend Transport; Wed, 4 Nov 2015 18:35:44 -0800 Received: from xhacker.marvell.com (unknown [10.37.135.134]) by maili.marvell.com (Postfix) with ESMTP id C80E93F7040; Wed, 4 Nov 2015 18:35:43 -0800 (PST) From: Jisheng Zhang To: , , Subject: [PATCH v3] clocksource/drivers/dw_apb_timer_of: Implement ARM delay timer Date: Thu, 5 Nov 2015 10:32:06 +0800 Message-ID: <1446690726-2024-1-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.6.2 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2015-11-05_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1511050037 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151104_183629_506895_2AE8221E X-CRM114-Status: GOOD ( 14.64 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jisheng Zhang , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Implement an ARM delay timer to be used for udelay(). This allows us to skip the delay loop calibration at boot on Marvell BG2, BG2Q, BG2CD platforms. And after this patch, udelay() will be unaffected by CPU frequency changes. Note: Although in case there are several possible delay timers, we may not select the "best" delay timer. Take one Marvell Berlin platform for example: we have arch timer and dw-apb timer. The arch timer freq is 25MHZ while the dw-apb timer freq is 100MHZ, current selection would choose the dw-apb timer. But the dw apb timer is on the APB bus while arch timer sits in CPU, the cost of accessing the apb timer is higher than the arch timer. We could introduce "rating" concept to delay timer, but this approach "brings a lot of complexity and workarounds in the code for a small benefit" as pointed out by Daniel. Later, Arnd pointed out "However, we could argue that this actually doesn't matter at all, because the entire point of the ndelay()/ udelay()/mdelay() functions is to waste CPU cycles doing not much at all, so we can just as well waste them reading the timer register than spinning on the CPU reading the arch timer more often.", so we just simply register the dw apb base delay timer. Signed-off-by: Jisheng Zhang --- Since v2: - remove the patch to add rating support for register_current_timer_delay() - remove the patch to set arch_delay_timer rating - remove "rating" in dw apb timer Since v1: - add one patch to let register_current_timer_delay() to choose the the highest rating delay timer - add one patch to set arch_delay_timer rating as 400 - remove CONFIG_DW_APB_TIMER_BASED_DELAY option, use CONFIG_ARM instead. - change the commit msg as "clocksource/drivers/abc: Foo...." drivers/clocksource/dw_apb_timer_of.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c index a19a3f6..860843c 100644 --- a/drivers/clocksource/dw_apb_timer_of.c +++ b/drivers/clocksource/dw_apb_timer_of.c @@ -16,6 +16,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ +#include #include #include #include @@ -130,6 +131,17 @@ static void __init init_sched_clock(void) sched_clock_register(read_sched_clock, 32, sched_rate); } +#ifdef CONFIG_ARM +static unsigned long dw_apb_delay_timer_read(void) +{ + return ~readl_relaxed(sched_io_base); +} + +static struct delay_timer dw_apb_delay_timer = { + .read_current_timer = dw_apb_delay_timer_read, +}; +#endif + static int num_called; static void __init dw_apb_timer_init(struct device_node *timer) { @@ -142,6 +154,10 @@ static void __init dw_apb_timer_init(struct device_node *timer) pr_debug("%s: found clocksource timer\n", __func__); add_clocksource(timer); init_sched_clock(); +#ifdef CONFIG_ARM + dw_apb_delay_timer.freq = sched_rate; + register_current_timer_delay(&dw_apb_delay_timer); +#endif break; default: break;