From patchwork Wed Nov 11 22:18:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 7598381 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0CDB09F2E9 for ; Wed, 11 Nov 2015 22:25:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1F368204A9 for ; Wed, 11 Nov 2015 22:25:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4401F201DD for ; Wed, 11 Nov 2015 22:25:09 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZwdmH-0000bZ-Pk; Wed, 11 Nov 2015 22:22:05 +0000 Received: from mail-pa0-x235.google.com ([2607:f8b0:400e:c03::235]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZwdkD-0006CR-D2 for linux-arm-kernel@lists.infradead.org; Wed, 11 Nov 2015 22:20:11 +0000 Received: by pacdm15 with SMTP id dm15so42812007pac.3 for ; Wed, 11 Nov 2015 14:19:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro_org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XU9aN9LaMJiyyrlFifbwqbrmv90C2HDPwO5wDUD78D4=; b=ZUvCTTBYJWiTEJg34q0Iu0YN24dyVqGoIW7qXNKqeu7hU3oA/6PvgUlFu62xP01vkv vgzYtnTt4GzlCSgrk9VssAWuv5gbdka5Of+FRsj8Qpf1FoXzBaEbzSzBQiCnDF8NbIQC oopRJQXql74D+vwUUXJqMZsBkqaObO38gcudJBMQInLiWOw7+mV0pH72GlUMh07C/J5u mdf5JItKdOAdQ3Xr5pm0+ggXjmncNh670qmw/kSK+H6kubp4ePa2mVkd7mCt7QYHfZKM SzDRDEp/4Et64kf7EXpXcw1DM0E7bfzQU5gRXSEl62LfRT76egH6WD/7SHQ0FFf0vmFW 8TBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XU9aN9LaMJiyyrlFifbwqbrmv90C2HDPwO5wDUD78D4=; b=W/LRMfInk5NNZkk2BJy5GaZb2BRaZnWbmfKASxKDlxqBiHeJf+9rozDLu+gm3/7fS7 74XGMB9EKHRz/t83t3o+iXOmJl057nfzc2VR46RHCM8Lv3gwBQcQx2EHOnZOTZFzHz5D e3aHxVFuGqW54qKTucmxuYaDePUQgYkZp/psRZEC1Sygq0VA8IlyKLyS5/CC/ao4ZUZg 8EQf6hdQ565uRMv/+inSnLldHv9BGQ4yUhSUgS7Wvizep9+BophrNINJp5LVXQJVcZb9 SUyKxBbUk31c9mQuvW02hkCb/zKrC6rLQyA2womk2S1eC4EbN66NINdxZAEMiK7bhSRN fqYg== X-Gm-Message-State: ALoCoQnhwSGe3O+cLB/vP4Ps1NleALVMhmDnoxmOVjZ58YoREM4aNIym9+rAFNVaoqHM6/Fl1S3t X-Received: by 10.66.217.234 with SMTP id pb10mr17829777pac.148.1447280378557; Wed, 11 Nov 2015 14:19:38 -0800 (PST) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id h10sm11156697pat.7.2015.11.11.14.19.37 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Nov 2015 14:19:38 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net, nicolas.pitre@linaro.org Subject: [PATCH V3 12/26] coresight: etm3x: consolidating initial config Date: Wed, 11 Nov 2015 15:18:02 -0700 Message-Id: <1447280296-19147-13-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1447280296-19147-1-git-send-email-mathieu.poirier@linaro.org> References: <1447280296-19147-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151111_141957_746405_D2A6CFAC X-CRM114-Status: GOOD ( 13.11 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, mathieu.poirier@linaro.org, pawel.moll@arm.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, fainelli@broadcom.com, adrian.hunter@intel.com, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There is really no point in having two functions to take care of doing the initials tracer configuration. As such moving everything to 'etm_set_default()'. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm3x.c | 37 ++++++++++----------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 4c54e104b610..e973e4d13bcb 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -41,7 +41,6 @@ module_param_named(boot_enable, boot_enable, int, S_IRUGO); /* The number of ETM/PTM currently registered */ static int etm_count; static struct etm_drvdata *etmdrvdata[NR_CPUS]; -static void etm_init_default_data(struct etm_config *config); /* * Memory mapped writes to clear os lock are not supported on some processors @@ -199,7 +198,7 @@ struct etm_config *get_etm_config(struct etm_drvdata *drvdata) return NULL; /* Set default config */ - etm_init_default_data(config); + etm_set_default(config); drvdata->config = config; out: return drvdata->config; @@ -212,6 +211,19 @@ void etm_set_default(struct etm_config *config) if (WARN_ON_ONCE(!config)) return; + /* + * Taken verbatim from the TRM: + * + * To trace all memory: + * set bit [24] in register 0x009, the ETMTECR1, to 1 + * set all other bits in register 0x009, the ETMTECR1, to 0 + * set all bits in register 0x007, the ETMTECR2, to 0 + * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). + */ + config->enable_ctrl1 = BIT(24); + config->enable_ctrl2 = 0x0; + config->enable_event = ETM_HARD_WIRE_RES_A; + config->trigger_event = ETM_DEFAULT_EVENT_VAL; config->enable_event = ETM_HARD_WIRE_RES_A; @@ -605,27 +617,6 @@ static void etm_init_arch_data(void *info) CS_LOCK(drvdata->base); } -static void etm_init_default_data(struct etm_config *config) -{ - if (WARN_ON_ONCE(!config)) - return; - - etm_set_default(config); - - /* - * Taken verbatim from the TRM: - * - * To trace all memory: - * set bit [24] in register 0x009, the ETMTECR1, to 1 - * set all other bits in register 0x009, the ETMTECR1, to 0 - * set all bits in register 0x007, the ETMTECR2, to 0 - * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). - */ - config->enable_ctrl1 = BIT(24); - config->enable_ctrl2 = 0x0; - config->enable_event = ETM_HARD_WIRE_RES_A; -} - static void etm_init_trace_id(struct etm_drvdata *drvdata) { /*