| Message ID | 1447764885-23100-5-git-send-email-tiffany.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Nov 17, 2015 at 08:54:41PM +0800, Tiffany Lin wrote: > add a DT binding documentation of Video Encoder for the > MT8173 SoC from Mediatek. > > Signed-off-by: Tiffany Lin <tiffany.lin@mediatek.com> > --- > .../devicetree/bindings/media/mediatek-vcodec.txt | 58 ++++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek-vcodec.txt > > diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > new file mode 100644 > index 0000000..fea4d7c > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > @@ -0,0 +1,58 @@ > +Mediatek Video Codec > + > +Mediatek Video Codec is the video codec hw present in Mediatek SoCs which > +supports high resolution encoding functionalities. > + > +Required properties: > +- compatible : "mediatek,mt8173-vcodec-enc" for encoder > +- reg : Physical base address of the video codec registers and length of > + memory mapped region. > +- interrupts : interrupt number to the cpu. > +- larb : must contain the larbes of current platform What is this? > +- clocks : list of clock specifiers, corresponding to entries in > + the clock-names property; > +- clock-names: must contain "vencpll", "venc_lt_sel", "vcodecpll_370p5_ck" > +- iommus : list of iommus specifiers should be enabled for hw encode. > + There are 2 cells needed to enable/disable iommu. > + The first one is local arbiter index(larbid), and the other is port > + index(portid) within local arbiter. Specifies the larbid and portid > + as defined in dt-binding/memory/mt8173-larb-port.h. > +- vpu : the node of video processor unit This should be prefixed with mediatek. > + > +Example: > +vcodec_enc: vcodec@0x18002000 { > + compatible = "mediatek,mt8173-vcodec-enc"; > + reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ > + <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ > + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, > + <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; > + larb = <&larb3>, > + <&larb5>; > + iommus = <&iommu M4U_LARB3_ID M4U_PORT_VENC_RCPU>, > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REC>, > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_BSDMA>, > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_SV_COMV>, > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_RD_COMV>, > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_CUR_LUMA>, > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_CUR_CHROMA>, > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REF_LUMA>, > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REF_CHROMA>, > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_NBM_RDMA>, > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_NBM_WDMA>, > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_RCPU_SET2>, > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REC_FRM_SET2>, > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_BSDMA_SET2>, > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_SV_COMA_SET2>, > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_RD_COMA_SET2>, > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_CUR_LUMA_SET2>, > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_CUR_CHROMA_SET2>, > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REF_LUMA_SET2>, > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REC_CHROMA_SET2>; > + vpu = <&vpu>; > + clocks = <&apmixedsys CLK_APMIXED_VENCPLL>, > + <&topckgen CLK_TOP_VENC_LT_SEL>, > + <&topckgen CLK_TOP_VCODECPLL_370P5>; > + clock-names = "vencpll", > + "venc_lt_sel", > + "vcodecpll_370p5_ck"; > + }; > -- > 1.7.9.5 >
Hi Rob, On Tue, 2015-11-17 at 13:41 -0600, Rob Herring wrote: > On Tue, Nov 17, 2015 at 08:54:41PM +0800, Tiffany Lin wrote: > > add a DT binding documentation of Video Encoder for the > > MT8173 SoC from Mediatek. > > > > Signed-off-by: Tiffany Lin <tiffany.lin@mediatek.com> > > --- > > .../devicetree/bindings/media/mediatek-vcodec.txt | 58 ++++++++++++++++++++ > > 1 file changed, 58 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/media/mediatek-vcodec.txt > > > > diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > > new file mode 100644 > > index 0000000..fea4d7c > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > > @@ -0,0 +1,58 @@ > > +Mediatek Video Codec > > + > > +Mediatek Video Codec is the video codec hw present in Mediatek SoCs which > > +supports high resolution encoding functionalities. > > + > > +Required properties: > > +- compatible : "mediatek,mt8173-vcodec-enc" for encoder > > +- reg : Physical base address of the video codec registers and length of > > + memory mapped region. > > +- interrupts : interrupt number to the cpu. > > +- larb : must contain the larbes of current platform > > What is this? Resend due to previous mail has html format and reject by some mail servers. This is SMI (Smart Multimedia Interface) Local Arbiter. MT8173 has different local arbiters (larb). Please see http://lists.linuxfoundation.org/pipermail/iommu/2015-October/014587.html Video Encoder HW has it's local arbiter (larb), by configure ports in this larb, we can have encoder HW go through the m4u to talk with EMI. We will change it to mediatek,larb in next version. > > > +- clocks : list of clock specifiers, corresponding to entries in > > + the clock-names property; > > +- clock-names: must contain "vencpll", "venc_lt_sel", "vcodecpll_370p5_ck" > > +- iommus : list of iommus specifiers should be enabled for hw encode. > > + There are 2 cells needed to enable/disable iommu. > > + The first one is local arbiter index(larbid), and the other is port > > + index(portid) within local arbiter. Specifies the larbid and portid > > + as defined in dt-binding/memory/mt8173-larb-port.h. > > +- vpu : the node of video processor unit > > This should be prefixed with mediatek. We will prefix it with mediatek in next version. > > > + > > +Example: > > +vcodec_enc: vcodec@0x18002000 { > > + compatible = "mediatek,mt8173-vcodec-enc"; > > + reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ > > + <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ > > + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, > > + <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; > > + larb = <&larb3>, > > + <&larb5>; > > + iommus = <&iommu M4U_LARB3_ID M4U_PORT_VENC_RCPU>, > > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REC>, > > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_BSDMA>, > > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_SV_COMV>, > > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_RD_COMV>, > > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_CUR_LUMA>, > > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_CUR_CHROMA>, > > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REF_LUMA>, > > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REF_CHROMA>, > > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_NBM_RDMA>, > > + <&iommu M4U_LARB3_ID M4U_PORT_VENC_NBM_WDMA>, > > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_RCPU_SET2>, > > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REC_FRM_SET2>, > > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_BSDMA_SET2>, > > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_SV_COMA_SET2>, > > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_RD_COMA_SET2>, > > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_CUR_LUMA_SET2>, > > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_CUR_CHROMA_SET2>, > > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REF_LUMA_SET2>, > > + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REC_CHROMA_SET2>; > > + vpu = <&vpu>; > > + clocks = <&apmixedsys CLK_APMIXED_VENCPLL>, > > + <&topckgen CLK_TOP_VENC_LT_SEL>, > > + <&topckgen CLK_TOP_VCODECPLL_370P5>; > > + clock-names = "vencpll", > > + "venc_lt_sel", > > + "vcodecpll_370p5_ck"; > > + }; > > -- > > 1.7.9.5 > > best regards, Tiffany
diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt new file mode 100644 index 0000000..fea4d7c --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt @@ -0,0 +1,58 @@ +Mediatek Video Codec + +Mediatek Video Codec is the video codec hw present in Mediatek SoCs which +supports high resolution encoding functionalities. + +Required properties: +- compatible : "mediatek,mt8173-vcodec-enc" for encoder +- reg : Physical base address of the video codec registers and length of + memory mapped region. +- interrupts : interrupt number to the cpu. +- larb : must contain the larbes of current platform +- clocks : list of clock specifiers, corresponding to entries in + the clock-names property; +- clock-names: must contain "vencpll", "venc_lt_sel", "vcodecpll_370p5_ck" +- iommus : list of iommus specifiers should be enabled for hw encode. + There are 2 cells needed to enable/disable iommu. + The first one is local arbiter index(larbid), and the other is port + index(portid) within local arbiter. Specifies the larbid and portid + as defined in dt-binding/memory/mt8173-larb-port.h. +- vpu : the node of video processor unit + +Example: +vcodec_enc: vcodec@0x18002000 { + compatible = "mediatek,mt8173-vcodec-enc"; + reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ + <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; + larb = <&larb3>, + <&larb5>; + iommus = <&iommu M4U_LARB3_ID M4U_PORT_VENC_RCPU>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REC>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_BSDMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_SV_COMV>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_RD_COMV>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_CUR_LUMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_CUR_CHROMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REF_LUMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REF_CHROMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_NBM_RDMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_NBM_WDMA>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_RCPU_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REC_FRM_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_BSDMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_SV_COMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_RD_COMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_CUR_LUMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_CUR_CHROMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REF_LUMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REC_CHROMA_SET2>; + vpu = <&vpu>; + clocks = <&apmixedsys CLK_APMIXED_VENCPLL>, + <&topckgen CLK_TOP_VENC_LT_SEL>, + <&topckgen CLK_TOP_VCODECPLL_370P5>; + clock-names = "vencpll", + "venc_lt_sel", + "vcodecpll_370p5_ck"; + };
add a DT binding documentation of Video Encoder for the MT8173 SoC from Mediatek. Signed-off-by: Tiffany Lin <tiffany.lin@mediatek.com> --- .../devicetree/bindings/media/mediatek-vcodec.txt | 58 ++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek-vcodec.txt