From patchwork Tue Nov 17 14:56:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlo Caione X-Patchwork-Id: 7637811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4EF719F392 for ; Tue, 17 Nov 2015 15:00:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2A78E2055C for ; Tue, 17 Nov 2015 15:00:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 018202053E for ; Tue, 17 Nov 2015 15:00:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZyhiN-0003PZ-Mw; Tue, 17 Nov 2015 14:58:35 +0000 Received: from mail-wm0-x234.google.com ([2a00:1450:400c:c09::234]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZyhhC-0002ln-QX for linux-arm-kernel@lists.infradead.org; Tue, 17 Nov 2015 14:57:27 +0000 Received: by wmdw130 with SMTP id w130so158547203wmd.0 for ; Tue, 17 Nov 2015 06:57:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=7Mdy0LStoXx3b4PXRFxrVlOqsZPno6gfsh91Uktqckc=; b=0xwgMW3MulixLF3WH72NSyErONjOJ2ICbIiX90f550vg3dwQj/CtJ2mIKu2318Qbmt GNUW+ORtCaBxPteXpLm48UKn4mjXgTkXnvPLfwAtUYh2DJA1BPou3cYFy+2BnImuc6iT XcExctgWNEhtau7BdOc79P5WNOXNLxujryLFWx3wEOTPdSKpgvuzjHYG0+/rKsbcA49s yhF2YATQpmaHFC5EVEUZXmdiW0ydC3mg6eZLdWIdM1eVvCUemOUh5xLxeHiw6pCdOZ+4 Q6ZQtkM+StKXJsecLb3KnW1wFe7C2wRvD917JosHCXq8vlR2uFTRq7cCS+NT95R9Igwc 98mA== X-Received: by 10.194.134.3 with SMTP id pg3mr48654523wjb.63.1447772224297; Tue, 17 Nov 2015 06:57:04 -0800 (PST) Received: from localhost.localdomain ([212.91.95.170]) by smtp.gmail.com with ESMTPSA id b84sm22578986wmh.15.2015.11.17.06.57.03 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 17 Nov 2015 06:57:03 -0800 (PST) From: Carlo Caione To: robh+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, linux@arm.linux.org.uk, linux-meson@googlegroups.com, drake@endlessm.com, jerry.cao@amlogic.com, victor.wan@amlogic.com, pawel.moll@arm.com, arnd@arndb.de Subject: [PATCH 6/7] ARM: meson8b: Add SMP bringup code Date: Tue, 17 Nov 2015 15:56:41 +0100 Message-Id: <1447772202-12418-7-git-send-email-carlo@caione.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1447772202-12418-1-git-send-email-carlo@caione.org> References: <1447772202-12418-1-git-send-email-carlo@caione.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151117_065723_294021_3E28E6D5 X-CRM114-Status: GOOD ( 21.66 ) X-Spam-Score: -2.4 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Carlo Caione MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Carlo Caione This adds the necessary SMP-operations and startup code to use the additional cores on the Amlogic Meson8b SoCs. Signed-off-by: Carlo Caione --- arch/arm/mach-meson/Kconfig | 1 + arch/arm/mach-meson/Makefile | 1 + arch/arm/mach-meson/platsmp.c | 228 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 230 insertions(+) create mode 100644 arch/arm/mach-meson/platsmp.c diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 5d56f86..e171744 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -6,6 +6,7 @@ menuconfig ARCH_MESON select CACHE_L2X0 select PINCTRL select PINCTRL_MESON + select HAVE_ARM_SCU if SMP if ARCH_MESON diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index 9d7380e..bc26c85 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_ARCH_MESON) += meson.o +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c new file mode 100644 index 0000000..37c9102 --- /dev/null +++ b/arch/arm/mach-meson/platsmp.c @@ -0,0 +1,228 @@ +/* + * Copyright (C) 2015 Carlo Caione + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MESON_CPU_CTRL_REG (0x00) +#define MESON_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2)) + +#define MESON_CPU_AO_RTI_PWR_A9_CNTL0 (0x00) +#define MESON_CPU_AO_RTI_PWR_A9_CNTL1 (0x04) +#define MESON_CPU_AO_RTI_PWR_A9_MEM_PD0 (0x14) + +#define MESON_CPU_PWR_A9_CNTL0_M(c) (0x03 << ((c * 2) + 16)) +#define MESON_CPU_PWR_A9_CNTL1_M(c) (0x03 << ((c + 1) << 1)) +#define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4))) +#define MESON_CPU_PWR_A9_CNTL1_ST(c) (0x01 << (c + 16)) + +static void __iomem *sram_base; +static void __iomem *scu_base; +static struct regmap *pmu; + +static void __init meson8b_smp_prepare_cpus(unsigned int max_cpus) +{ + static struct device_node *node; + + /* SMP SRAM */ + node = of_find_compatible_node(NULL, NULL, "amlogic,meson8b-smp-sram"); + if (!node) { + pr_err("Missing SRAM node\n"); + return; + } + + sram_base = of_iomap(node, 0); + if (!sram_base) { + pr_err("Couldn't map SRAM registers\n"); + return; + } + + /* PMU */ + pmu = syscon_regmap_lookup_by_compatible("amlogic,meson8b-pmu"); + if (IS_ERR(pmu)) { + pr_err("Couldn't map PMU registors\n"); + return; + } + + /* SCU */ + node = of_find_compatible_node(NULL, NULL, "arm,cortex-a5-scu"); + if (!node) { + pr_err("Missing SCU node\n"); + return; + } + + scu_base = of_iomap(node, 0); + if (!scu_base) { + pr_err("Couln't map SCU registers\n"); + return; + } + + scu_enable(scu_base); +} + +static struct reset_control *meson_get_core_reset(int cpu) +{ + struct device_node *np; + + np = of_get_cpu_node(cpu, 0); + + return of_reset_control_get(np, NULL); +} + +static int meson8b_set_cpu_power_ctrl(unsigned int cpu, bool is_power_on) +{ + struct reset_control *rstc = meson_get_core_reset(cpu); + int ret; + u32 val; + + if (is_power_on) { + + /* CPU power UP */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, + MESON_CPU_PWR_A9_CNTL0_M(cpu), 0); + if (ret < 0) { + pr_err("Couldn't power up the CPU\n"); + return ret; + } + + udelay(5); + + /* Reset enable */ + reset_control_assert(rstc); + + /* Memory power UP */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0, + MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0); + if (ret < 0) { + pr_err("Couldn't power up the memory\n"); + return ret; + } + + /* Wake up CPU */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, + MESON_CPU_PWR_A9_CNTL1_M(cpu), 0); + if (ret < 0) { + pr_err("Couldn't wake up the CPU\n"); + return ret; + } + + udelay(10); + + val = 0; + while (!(val & MESON_CPU_PWR_A9_CNTL1_ST(cpu))) { + ret = regmap_read(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, &val); + if (ret < 0) { + pr_err("CPU wake up failed\n"); + return ret; + } + } + + /* Isolation disable */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, + BIT(cpu), 0); + if (ret < 0) { + pr_err("Error when disabling isolation\n"); + return ret; + } + + /* Reset disable */ + reset_control_deassert(rstc); + + } else { + + /* CPU power DOWN */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, + MESON_CPU_PWR_A9_CNTL0_M(cpu), 0x3); + if (ret < 0) { + pr_err("Couldn't power down the CPU\n"); + return ret; + } + + /* Isolation enable */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL0, + BIT(cpu), 0x3); + if (ret < 0) { + pr_err("Error when enabling isolation\n"); + return ret; + } + + udelay(10); + + /* Sleep status */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_CNTL1, + MESON_CPU_PWR_A9_CNTL1_M(cpu), 0x3); + if (ret < 0) { + pr_err("Couldn't change sleep status\n"); + return ret; + } + + /* Memory power DOWN */ + ret = regmap_update_bits(pmu, MESON_CPU_AO_RTI_PWR_A9_MEM_PD0, + MESON_CPU_PWR_A9_MEM_PD0_M(cpu), 0xf); + if (ret < 0) { + pr_err("Couldn't power down the memory\n"); + return ret; + } + } + + return 0; +} + +static int meson8b_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + int ret; + u32 reg; + + ret = meson8b_set_cpu_power_ctrl(cpu, 1); + if (ret < 0) + return ret; + + timeout = jiffies + (10 * HZ); + while (readl(sram_base + MESON_CPU_CTRL_ADDR_REG(cpu))) + if (!time_before(jiffies, timeout)) + return -EPERM; + + udelay(100); + writel(virt_to_phys(secondary_startup), sram_base + MESON_CPU_CTRL_ADDR_REG(cpu)); + + reg = readl(sram_base + MESON_CPU_CTRL_REG); + reg |= (BIT(cpu) | BIT(0)); + writel(reg, sram_base + MESON_CPU_CTRL_REG); + + return 0; +} + +static void meson8b_smp_secondary_init(unsigned int cpu) +{ + scu_power_mode(scu_base, SCU_PM_NORMAL); +} + +static struct smp_operations meson8b_smp_ops __initdata = { + .smp_prepare_cpus = meson8b_smp_prepare_cpus, + .smp_boot_secondary = meson8b_smp_boot_secondary, + .smp_secondary_init = meson8b_smp_secondary_init, +}; + +CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops);