From patchwork Tue Nov 17 18:03:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 7640271 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0A808BF90C for ; Tue, 17 Nov 2015 18:06:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 15CC320462 for ; Tue, 17 Nov 2015 18:06:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 081382047D for ; Tue, 17 Nov 2015 18:06:43 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zykcf-0001wa-Dt; Tue, 17 Nov 2015 18:04:53 +0000 Received: from eu-smtp-delivery-143.mimecast.com ([146.101.78.143]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zykbw-0001dJ-BI for linux-arm-kernel@lists.infradead.org; Tue, 17 Nov 2015 18:04:12 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-5-JvBmqui_TlGPZWmAOrcsnA-11; Tue, 17 Nov 2015 18:03:46 +0000 Received: from e106634-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 17 Nov 2015 18:03:43 +0000 From: "Suzuki K. Poulose" To: linux-arm-kernel@lists.infradead.org Subject: [PATCHv3 5/5] arm-cci: CCI-500: Work around PMU counter writes Date: Tue, 17 Nov 2015 18:03:27 +0000 Message-Id: <1447783407-18027-6-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1447783407-18027-1-git-send-email-suzuki.poulose@arm.com> References: <1447783407-18027-1-git-send-email-suzuki.poulose@arm.com> X-OriginalArrivalTime: 17 Nov 2015 18:03:43.0041 (UTC) FILETIME=[4BAA2B10:01D12162] X-MC-Unique: JvBmqui_TlGPZWmAOrcsnA-11 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151117_100408_803499_3D063C1B X-CRM114-Status: GOOD ( 12.95 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, punit.agrawal@arm.com, arm@kernel.org, "Suzuki K. Poulose" , linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The CCI PMU driver sets the event counter to the half of the maximum value(2^31) it can count before we start the counters via pmu_event_set_period(). This is done to give us the best chance to handle the overflow interrupt, taking care of extreme interrupt latencies. However, CCI-500 comes with advanced power saving schemes, which disables the clock to the event counters unless the counters are enabled to count (PMCR.CEN). This prevents the driver from writing the period to the counters before starting them. Also, there is no way we can reset the individual event counter to 0 (PMCR.RST resets all the counters, losing their current readings). However the value of the counter is preserved and could be read back, when the counters are not enabled. So we cannot reliably use the counters and compute the number of events generated during the sampling period since we don't have the value of the counter at start. This patch works around this issue by changing writes to the counter with the following steps. 1) Disable all the counters (remembering any counters which were enabled) 2) Save the current event and program the target counter to count an invalid event, which by spec is guaranteed to not-generate any events. 3) Enable the target counter. 4) Enable the CCI PMU 5) Write to the target counter. 6) Disable the CCI PMU and the target counter 7) Restore the event back on the target counter. 8) Restore the status of the all the counters Cc: Punit Agrawal Cc: Mark Rutland Signed-off-by: Suzuki K. Poulose --- drivers/bus/arm-cci.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 88b612f..6020a02 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -835,6 +835,52 @@ static void __pmu_write_counter(struct cci_pmu *cci_pmu, u32 value, int idx) pmu_write_register(cci_pmu, value, idx, CCI_PMU_CNTR); } +#ifdef CONFIG_ARM_CCI500_PMU + +/* + * CCI-500 has advanced power saving policies, which could gate the + * clocks to the PMU counters, which makes the writes to them ineffective. + * The only way to write to those counters is when the global counters + * are enabled and the particular counter is enabled. + * + * So we do the following : + * + * 1) Disable all the PMU counters, saving their current state + * 2) Save the programmed event, and write an invalid event code + * to the event control register for the counter, so that the + * counters are not modified. + * 3) Enable the counter control for the counter. + * 4) Enable the global PMU profiling + * 5) Set the counter value + * 6) Disable the counter, global PMU. + * 7) Restore the event in the target counter + * 8) Restore the status of the rest of the counters. + * + * We choose an event code which has very little chances of getting + * assigned a valid code for step(2). We use the highest possible + * event code (0x1f) for the master interface 0. + */ +#define CCI500_INVALID_EVENT ((CCI500_PORT_M0 << CCI500_PMU_EVENT_SOURCE_SHIFT) | \ + (CCI500_PMU_EVENT_CODE_MASK << CCI500_PMU_EVENT_CODE_SHIFT)) +static void cci500_pmu_write_counter(struct cci_pmu *cci_pmu, u32 value, int idx) +{ + unsigned long mask[BITS_TO_LONGS(cci_pmu->num_cntrs)]; + u32 event; + + pmu_disable_counters(cci_pmu, mask); + event = pmu_get_event(cci_pmu, idx); + pmu_set_event(cci_pmu, idx, CCI500_INVALID_EVENT); + pmu_enable_counter(cci_pmu, idx); + __cci_pmu_enable(); + __pmu_write_counter(cci_pmu, value, idx); + __cci_pmu_disable(); + pmu_disable_counter(cci_pmu, idx); + pmu_set_event(cci_pmu, idx, event); + pmu_restore_counters(cci_pmu, mask); +} + +#endif /* CONFIG_ARM_CCI500_PMU */ + static void pmu_write_counter(struct perf_event *event, u32 value) { struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); @@ -1422,6 +1468,7 @@ static struct cci_pmu_model cci_pmu_models[] = { }, }, .validate_hw_event = cci500_validate_hw_event, + .write_counter = cci500_pmu_write_counter, }, #endif };