From patchwork Thu Nov 19 15:53:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Weseloh X-Patchwork-Id: 7658551 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BD35B9F2EC for ; Thu, 19 Nov 2015 15:56:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E835120676 for ; Thu, 19 Nov 2015 15:56:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 16C0A2066A for ; Thu, 19 Nov 2015 15:56:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZzRXZ-0008JG-V1; Thu, 19 Nov 2015 15:54:29 +0000 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZzRXM-0007O7-Kj for linux-arm-kernel@lists.infradead.org; Thu, 19 Nov 2015 15:54:18 +0000 Received: by wmww144 with SMTP id w144so122472427wmw.0 for ; Thu, 19 Nov 2015 07:53:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IZcFwQYjYO8iYctb6OMEcskBhYts5HJQgUUvOI4Y19o=; b=qSiWmxRkZszcMHXpTmaVCFB3NQ1PzJ7eDiOPxUc7fqiJ2b6y3Reoymz46Fk0beL55s 0KkgLZi0Ppec+222qGpJAjiKfW1cxKJD5MO+sTvidK46WxUS427v/xX6fLc9X6mb9O5s ZDHJiJIbel6uaczB4lEmZYTA9MeDreWGCa7oLD5CnmMpeVxdxjULI7ZVvrvEak0KU9yb hRNx6nzabUz9u1wb4aru3YjXa4O1dA3XIGPD3JmPNTN2lOQfAPsMmf5zkYq513mtQ+ji nwYo94TyXDPr8yU49yELk6p52EE5VV6EhbynGcD5BuIIHuZJkMH8d38VTDISA5GyKcf4 VdZQ== X-Received: by 10.194.91.234 with SMTP id ch10mr10199264wjb.69.1447948434812; Thu, 19 Nov 2015 07:53:54 -0800 (PST) Received: from speedy.fritz.box (p578E993C.dip0.t-ipconnect.de. [87.142.153.60]) by smtp.gmail.com with ESMTPSA id u17sm8965000wmd.8.2015.11.19.07.53.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 19 Nov 2015 07:53:53 -0800 (PST) From: Marcus Weseloh To: linux-sunxi@googlegroups.com Subject: [PATCH] spi: dts: sun4i: Add support for inter-word wait cycles using the SPI Wait Clock Register Date: Thu, 19 Nov 2015 16:53:42 +0100 Message-Id: <1447948422-4915-2-git-send-email-mweseloh42@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1447948422-4915-1-git-send-email-mweseloh42@gmail.com> References: <1447948422-4915-1-git-send-email-mweseloh42@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151119_075417_142505_DCBE8091 X-CRM114-Status: GOOD ( 15.25 ) X-Spam-Score: -2.5 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , Mark Brown , linux-kernel@vger.kernel.org, Rob Herring , linux-spi@vger.kernel.org, Marcus Weseloh , Kumar Gala , Maxime Ripard , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds support and documentation for a new slave device property "sun4i,spi-wdelay" that allows to set the SPI Wait Clock Register per device / transfer. The SPI hardware will wait the specified amount of SPI clock periods (plus a constant 3 clock periods) before transmitting the next word. The constant additional 3 clock periods are not documented by the vendor and have been determined by analyzing the generated waveforms across many different transmission speeds. Signed-off-by: Marcus Weseloh --- Documentation/devicetree/bindings/spi/spi-sun4i.txt | 11 +++++++++++ drivers/spi/spi-sun4i.c | 7 +++++++ 2 files changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-sun4i.txt b/Documentation/devicetree/bindings/spi/spi-sun4i.txt index de827f5..9c4d723 100644 --- a/Documentation/devicetree/bindings/spi/spi-sun4i.txt +++ b/Documentation/devicetree/bindings/spi/spi-sun4i.txt @@ -10,6 +10,10 @@ Required properties: - "mod": the parent module clock - clock-names: Must contain the clock names described just above +Optional properties for slave devices: +- sun4i,spi-wdelay : delay between transmission of words, specified in number + of SPI clock periods (actual delay is wdelay + 3 clock periods) + Example: spi1: spi@01c06000 { @@ -21,4 +25,11 @@ spi1: spi@01c06000 { status = "disabled"; #address-cells = <1>; #size-cells = <0>; + + spi1_0 { + compatible = "example,dummy"; + reg = <0>; + spi-max-frequency = <1000000>; /* 1Mhz = 1us clock period */ + sun4i,spi-wdelay = <2>; /* delay 5us (2 + 3 clock periods) */ + }; }; diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c index f60a6d6..a8e39f1 100644 --- a/drivers/spi/spi-sun4i.c +++ b/drivers/spi/spi-sun4i.c @@ -19,6 +19,7 @@ #include #include #include +#include #include @@ -173,6 +174,7 @@ static int sun4i_spi_transfer_one(struct spi_master *master, unsigned int tx_len = 0; int ret = 0; u32 reg; + u32 wdelay = 0; /* We don't support transfer larger than the FIFO */ if (tfr->len > SUN4I_FIFO_DEPTH) @@ -261,6 +263,11 @@ static int sun4i_spi_transfer_one(struct spi_master *master, sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg); + /* Set optional inter-word wait cycles */ + of_property_read_u32(spi->dev.of_node, "sun4i,spi-wdelay", + &wdelay); + sun4i_spi_write(sspi, SUN4I_WAIT_REG, (u16)wdelay); + /* Setup the transfer now... */ if (sspi->tx_buf) tx_len = tfr->len;