From patchwork Mon Nov 23 18:33:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 7685371 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6F3109F2E2 for ; Mon, 23 Nov 2015 18:55:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 56756207B6 for ; Mon, 23 Nov 2015 18:55:49 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 49DA5207A5 for ; Mon, 23 Nov 2015 18:55:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a0wFF-0004Hi-Bq; Mon, 23 Nov 2015 18:53:45 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a0wBw-0008TH-38 for linux-arm-kernel@bombadil.infradead.org; Mon, 23 Nov 2015 18:50:20 +0000 Received: from mail-pa0-x22c.google.com ([2607:f8b0:400e:c03::22c]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a0aMD-0004Ub-3D for linux-arm-kernel@lists.infradead.org; Sun, 22 Nov 2015 19:31:30 +0000 Received: by pacej9 with SMTP id ej9so198774135pac.2 for ; Mon, 23 Nov 2015 10:34:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BcCobha+Nff4NAawZgoFqF/m9Auy3bLkteXRfcVsBJM=; b=RAZ3XNiIOo0XlOWBB3M1hsyOongEKboHQqvvczNzQkaiu5bMOjc9N4Uclnf0+HQVTQ jkuNbaWNi1uWE33wKs0E2AbcY2t5CYrTO4YV10p+mCaTMtmCJQ4GL0f9SVsjvnfHPm9b FYLlvsfgPmYWW7zhdZ+cjfhKgsUx97jMTBWkSH2WYeoZVh7e04bBWIKOJ05u758H580K 05JouCNsNXcmS9uHEgyP6DY4GLfJMe8aAtGjhk2ba6o2GGcufE9JzG3PkUMd4jq7Z9Nb k62N42NxEm0tMm4ZhnLuGSyFD5+LAdPFhIFtFw2XDe6gr0A69y8PTWMzEB8lXRUdS6i/ 8zdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BcCobha+Nff4NAawZgoFqF/m9Auy3bLkteXRfcVsBJM=; b=S5oqNP6H1AQGzJ6EfJBLdIgszhFpf+KDX4t2gnXLJ5plKlu1U4UZKEYV33s/RQf+nd xZurYaQzYmBHtSzcqNjLJ1iLOQeZYm9AHiI7GF5gpiOhl+xzl1lHPQOoNvcB+2axi26P DD8SsCg6aEtMIjVT+woyxP03ZNagvZpt/oXUIltogmz2kKBLWLdMC6EI0Y1gEW/L+uSR ++hlBUaw44Lf9qZTfxOvbNe1+EeP2tUZnMrRSxBB836yj/xg9AQJPZlKWfKr8q5930Tt 6UZqvgYexcRN8NEKaQEv0yksw3xRtoRcR+ixGETTM76pJAItJ5FZmIPJ919Oty4S0JOs kpyw== X-Gm-Message-State: ALoCoQnjJNaqB38Vq4f5PU4+QtRmat8tGIddV7Ot6u/Ps2T9jKCBGi0k2rxP+XmTpif/R3xpsKnx X-Received: by 10.66.62.131 with SMTP id y3mr37313155par.104.1448303667523; Mon, 23 Nov 2015 10:34:27 -0800 (PST) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id r20sm10865186pfa.93.2015.11.23.10.34.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Nov 2015 10:34:26 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net, nicolas.pitre@linaro.org Subject: [RESEND PATCH V4 18/26] coresight: adding operation mode for sink->enable() Date: Mon, 23 Nov 2015 11:33:10 -0700 Message-Id: <1448303598-11249-19-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1448303598-11249-1-git-send-email-mathieu.poirier@linaro.org> References: <1448303598-11249-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151122_193129_481379_47742200 X-CRM114-Status: GOOD ( 21.55 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, pawel.moll@arm.com, linux-doc@vger.kernel.org, fainelli@broadcom.com, linux-kernel@vger.kernel.org, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adding an operation mode to sink->enable() API in order to prevent simultaneous access from different callers. TPIU and TMC won't be supplemented with the AUX area API immediately and as such ignore the new mode. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 31 +++++++++++++++++++++------ drivers/hwtracing/coresight/coresight-priv.h | 2 +- drivers/hwtracing/coresight/coresight-tmc.c | 2 +- drivers/hwtracing/coresight/coresight-tpiu.c | 2 +- drivers/hwtracing/coresight/coresight.c | 10 ++++----- include/linux/coresight.h | 2 +- 6 files changed, 33 insertions(+), 16 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 09e306361e4f..dc4d707b28aa 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -73,9 +73,9 @@ * @miscdev: specifics to handle "/dev/xyz.etb" entry. * @spinlock: only one at a time pls. * @reading: synchronise user space access to etb buffer. + * @mode: this ETB is being used. * @buf: area of memory where ETB buffer content gets sent. * @buffer_depth: size of @buf. - * @enable: this ETB is being used. * @trigger_cntr: amount of words to store after a trigger. */ struct etb_drvdata { @@ -86,9 +86,9 @@ struct etb_drvdata { struct miscdevice miscdev; spinlock_t spinlock; local_t reading; + local_t mode; u8 *buf; u32 buffer_depth; - bool enable; u32 trigger_cntr; }; @@ -133,18 +133,34 @@ static void etb_enable_hw(struct etb_drvdata *drvdata) CS_LOCK(drvdata->base); } -static int etb_enable(struct coresight_device *csdev) +static int etb_enable(struct coresight_device *csdev, u32 mode) { - struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + u32 val; unsigned long flags; + struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + val = local_cmpxchg(&drvdata->mode, + CS_MODE_DISABLED, mode); + /* + * When accessing from Perf, a HW buffer can be handled + * by a single trace entity. In sysFS mode many tracers + * can be logging to the same HW buffer. + */ + if (val == CS_MODE_PERF) + return -EBUSY; + + /* Nothing to do, the tracer is already enabled. */ + if (val == CS_MODE_SYSFS) + goto out; spin_lock_irqsave(&drvdata->spinlock, flags); etb_enable_hw(drvdata); - drvdata->enable = true; spin_unlock_irqrestore(&drvdata->spinlock, flags); +out: dev_info(drvdata->dev, "ETB enabled\n"); return 0; + } static void etb_disable_hw(struct etb_drvdata *drvdata) @@ -243,9 +259,10 @@ static void etb_disable(struct coresight_device *csdev) spin_lock_irqsave(&drvdata->spinlock, flags); etb_disable_hw(drvdata); etb_dump_hw(drvdata); - drvdata->enable = false; spin_unlock_irqrestore(&drvdata->spinlock, flags); + local_set(&drvdata->mode, CS_MODE_DISABLED); + dev_info(drvdata->dev, "ETB disabled\n"); } @@ -263,7 +280,7 @@ static void etb_dump(struct etb_drvdata *drvdata) unsigned long flags; spin_lock_irqsave(&drvdata->spinlock, flags); - if (drvdata->enable) { + if (local_read(&drvdata->mode) == CS_MODE_SYSFS) { etb_disable_hw(drvdata); etb_dump_hw(drvdata); etb_enable_hw(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 932f34a84d96..333eddaed339 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -62,7 +62,7 @@ static inline void CS_UNLOCK(void __iomem *addr) } void coresight_disable_path(struct list_head *path); -int coresight_enable_path(struct list_head *path); +int coresight_enable_path(struct list_head *path, u32 mode); struct coresight_device *coresight_get_sink(struct list_head *path); struct list_head *coresight_build_path(struct coresight_device *csdev); void coresight_release_path(struct list_head *path); diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 5e2a71767870..d7e83da7a621 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -265,7 +265,7 @@ static int tmc_enable(struct tmc_drvdata *drvdata, enum tmc_mode mode) return 0; } -static int tmc_enable_sink(struct coresight_device *csdev) +static int tmc_enable_sink(struct coresight_device *csdev, u32 mode) { struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index e19b86e61c38..0a09135382f6 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -70,7 +70,7 @@ static void tpiu_enable_hw(struct tpiu_drvdata *drvdata) CS_LOCK(drvdata->base); } -static int tpiu_enable(struct coresight_device *csdev) +static int tpiu_enable(struct coresight_device *csdev, u32 mode) { struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 47a4e109f700..52311e77da9d 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -121,13 +121,13 @@ static int coresight_find_link_outport(struct coresight_device *csdev, return 0; } -static int coresight_enable_sink(struct coresight_device *csdev) +static int coresight_enable_sink(struct coresight_device *csdev, u32 mode) { int ret; if (!csdev->enable) { if (sink_ops(csdev)->enable) { - ret = sink_ops(csdev)->enable(csdev); + ret = sink_ops(csdev)->enable(csdev, mode); if (ret) return ret; } @@ -283,7 +283,7 @@ void coresight_disable_path(struct list_head *path) } } -int coresight_enable_path(struct list_head *path) +int coresight_enable_path(struct list_head *path, u32 mode) { int ret = 0; @@ -296,7 +296,7 @@ int coresight_enable_path(struct list_head *path) switch (csdev->type) { case CORESIGHT_DEV_TYPE_SINK: case CORESIGHT_DEV_TYPE_LINKSINK: - ret = coresight_enable_sink(csdev); + ret = coresight_enable_sink(csdev, mode); if (ret) goto err; break; @@ -454,7 +454,7 @@ int coresight_enable(struct coresight_device *csdev) goto out; } - ret = coresight_enable_path(path); + ret = coresight_enable_path(path, CS_MODE_SYSFS); if (ret) goto err_path; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index f2148bc2bcfe..80b3465bd459 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -185,7 +185,7 @@ struct coresight_device { * @disable: disables the sink. */ struct coresight_ops_sink { - int (*enable)(struct coresight_device *csdev); + int (*enable)(struct coresight_device *csdev, u32 mode); void (*disable)(struct coresight_device *csdev); };