From patchwork Wed Nov 25 10:33:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Murzin X-Patchwork-Id: 7697251 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6F785C05CA for ; Wed, 25 Nov 2015 10:39:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 57A7C208E4 for ; Wed, 25 Nov 2015 10:39:38 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2662B208E1 for ; Wed, 25 Nov 2015 10:39:37 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a1XS3-0001S7-4R; Wed, 25 Nov 2015 10:37:27 +0000 Received: from eu-smtp-delivery-143.mimecast.com ([207.82.80.143]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a1XR4-0000r1-Ox for linux-arm-kernel@lists.infradead.org; Wed, 25 Nov 2015 10:36:30 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-24-F5VWHmbZRumat_2lu4dl_g-5; Wed, 25 Nov 2015 10:36:03 +0000 Received: from login1.euhpc.arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 25 Nov 2015 10:35:52 +0000 From: Vladimir Murzin To: arnd@arndb.de, linux@arm.linux.org.uk, gregkh@linuxfoundation.org, daniel.lezcano@linaro.org, tglx@linutronix.de, u.kleine-koenig@pengutronix.de, afaerber@suse.de, mcoquelin.stm32@gmail.com Subject: [RFC PATCH 02/10] clockevents/drivers: add MPS2 Timer driver Date: Wed, 25 Nov 2015 10:33:33 +0000 Message-Id: <1448447621-17900-3-git-send-email-vladimir.murzin@arm.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1448447621-17900-1-git-send-email-vladimir.murzin@arm.com> References: <1448447621-17900-1-git-send-email-vladimir.murzin@arm.com> X-OriginalArrivalTime: 25 Nov 2015 10:35:52.0885 (UTC) FILETIME=[0F1BBE50:01D1276D] X-MC-Unique: F5VWHmbZRumat_2lu4dl_g-5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151125_023627_288187_6F270E34 X-CRM114-Status: GOOD ( 12.38 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark.Rutland@arm.com, devicetree@vger.kernel.org, Pawel.Moll@arm.com, ijc+devicetree@hellion.org.uk, linux-api@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-serial@vger.kernel.org, galak@codeaurora.org, jslaby@suse.cz, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP MPS2 platform has simple 32 bits general purpose countdown timers. The driver uses the first detected timer as a clocksource and the rest of the timers as a clockevent Signed-off-by: Vladimir Murzin --- drivers/clocksource/Kconfig | 5 + drivers/clocksource/Makefile | 1 + drivers/clocksource/mps2-timer.c | 280 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 286 insertions(+) create mode 100644 drivers/clocksource/mps2-timer.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 71cfdf7..552ab54 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -136,6 +136,11 @@ config CLKSRC_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) select CLKSRC_MMIO +config CLKSRC_MPS2 + bool "Clocksource for MPS2 SoCs" + depends on OF && (ARM || COMPILE_TEST) + select CLKSRC_MMIO + config ARM_ARCH_TIMER bool select CLKSRC_OF if OF diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 56bd16e..7033b9c 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o obj-$(CONFIG_CLKSRC_STM32) += timer-stm32.o obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o obj-$(CONFIG_CLKSRC_LPC32XX) += time-lpc32xx.o +obj-$(CONFIG_CLKSRC_MPS2) += mps2-timer.o obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o diff --git a/drivers/clocksource/mps2-timer.c b/drivers/clocksource/mps2-timer.c new file mode 100644 index 0000000..77befe2 --- /dev/null +++ b/drivers/clocksource/mps2-timer.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2015 ARM Limited + * + * Author: Vladimir Murzin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TIMER_CTRL 0x0 +#define TIMER_CTRL_ENABLE BIT(0) +#define TIMER_CTRL_IE BIT(3) + +#define TIMER_VALUE 0x4 +#define TIMER_RELOAD 0x8 +#define TIMER_INT 0xc + +struct clockevent_mps2 { + void __iomem *reg; + u32 clock_count_per_tick; + struct clock_event_device clkevt; +}; + +static void __iomem *sched_clock_base; + +static u64 notrace mps2_sched_read(void) +{ + return ~readl_relaxed(sched_clock_base + TIMER_VALUE); +} + + +static inline struct clockevent_mps2 *to_mps2_clkevt(struct clock_event_device *c) +{ + return container_of(c, struct clockevent_mps2, clkevt); +} + +static void clockevent_mps2_writel(u32 val, struct clock_event_device *c, u32 offset) +{ + writel(val, to_mps2_clkevt(c)->reg + offset); +} + +static int mps2_timer_shutdown(struct clock_event_device *ce) +{ + clockevent_mps2_writel(0, ce, TIMER_RELOAD); + clockevent_mps2_writel(0, ce, TIMER_CTRL); + + return 0; +} + +static int mps2_timer_set_next_event(unsigned long next, struct clock_event_device *ce) +{ + clockevent_mps2_writel(next, ce, TIMER_VALUE); + clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL); + + return 0; +} + +static int mps2_timer_set_periodic(struct clock_event_device *ce) +{ + u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; + + clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_RELOAD); + clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_VALUE); + clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL); + + return 0; +} + +static irqreturn_t mps2_timer_interrupt(int irq, void *dev_id) +{ + struct clockevent_mps2 *ce = dev_id; + u32 status = readl(ce->reg + TIMER_INT); + + if (!status) + return IRQ_NONE; + + writel(1, ce->reg + TIMER_INT); + + ce->clkevt.event_handler(&ce->clkevt); + + return IRQ_HANDLED; +} + +static int __init mps2_clockevents_init(struct device_node *np) +{ + void __iomem *base; + struct clk *clk; + struct irqaction *ia; + struct clockevent_mps2 *ce; + u32 rate; + int irq, ret; + const char *name = "mps2-clkevt"; + + ret = of_property_read_u32(np, "clock-frequency", &rate); + + if (ret) { + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + pr_err("failed to get clock for clockevent: %d\n", ret); + goto err_clk_get; + } + + ret = clk_prepare_enable(clk); + if (ret) { + pr_err("failed to enable clock for clockevent: %d\n", ret); + clk_put(clk); + goto err_clk_enable; + } + + rate = clk_get_rate(clk); + } + + base = of_iomap(np, 0); + if (!base) { + ret = -EADDRNOTAVAIL; + pr_err("failed to map register for clockevent: %d\n", ret); + goto err_iomap; + } + + irq = irq_of_parse_and_map(np, 0); + if (!irq) { + ret = -ENOENT; + pr_err("failed to get irq for clockevent: %d\n", ret); + goto err_get_irq; + } + + ce = kzalloc(sizeof(struct clockevent_mps2), GFP_KERNEL); + if (!ce) { + ret = -ENOMEM; + pr_err("failed to allocate clockevent: %d\n", ret); + goto err_ce_alloc; + } + + ce->reg = base; + ce->clock_count_per_tick = DIV_ROUND_CLOSEST(rate, HZ); + ce->clkevt.irq = irq; + ce->clkevt.name = name; + ce->clkevt.rating = 200; + ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + ce->clkevt.cpumask = cpu_possible_mask; + ce->clkevt.set_state_shutdown = mps2_timer_shutdown, + ce->clkevt.set_state_periodic = mps2_timer_set_periodic, + ce->clkevt.set_state_oneshot = mps2_timer_shutdown, + ce->clkevt.set_next_event = mps2_timer_set_next_event; + + ia = kzalloc(sizeof(struct irqaction), GFP_KERNEL); + if (!ia) { + ret = -ENOMEM; + pr_err("failed to allocate irqaction: %d\n", ret); + goto err_ia_alloc; + } + + ia->name = name; + ia->flags = IRQF_TIMER; + ia->handler = mps2_timer_interrupt; + ia->dev_id = ce; + + writel(0, base + TIMER_CTRL); + + ret = setup_irq(irq, ia); + + if (ret) { + pr_err("failed to setup irq: %d\n", ret); + goto err_setup_irq; + } + + clockevents_config_and_register(&ce->clkevt, rate, 0xf, 0xffffffff); + + return 0; + +err_setup_irq: + kfree(ia); +err_ia_alloc: + kfree(ce); +err_ce_alloc: +err_get_irq: + iounmap(base); +err_iomap: + clk_disable_unprepare(clk); +err_clk_enable: + clk_put(clk); +err_clk_get: + return ret; +} + +static int mps2_clocksource_init(struct device_node *np) +{ + void __iomem *base; + struct clk *clk; + u32 rate; + int ret; + const char *name = "mps2-clksrc"; + + ret = of_property_read_u32(np, "clock-frequency", &rate); + + if (ret) { + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + pr_err("failed to get clock for clocksource: %d\n", ret); + goto err_clk_get; + } + + ret = clk_prepare_enable(clk); + if (ret) { + pr_err("failed to enable clock for clocksource: %d\n", ret); + clk_put(clk); + goto err_clk_enable; + } + + rate = clk_get_rate(clk); + } + + base = of_iomap(np, 0); + if (!base) { + ret = -EADDRNOTAVAIL; + pr_err("failed to map register for clocksource: %d\n", ret); + goto err_iomap; + } + + writel(0, base + TIMER_CTRL); + + writel(0xffffffff, base + TIMER_VALUE); + writel(0xffffffff, base + TIMER_RELOAD); + + writel(TIMER_CTRL_ENABLE, base + TIMER_CTRL); + + ret = clocksource_mmio_init(base + TIMER_VALUE, name, + rate, 200, 32, + clocksource_mmio_readl_down); + if (ret) { + pr_err("failed to init clocksource: %d\n", ret); + goto err_clocksource_init; + } + + sched_clock_base = base; + sched_clock_register(mps2_sched_read, 32, rate); + + return 0; + +err_clocksource_init: + iounmap(base); +err_iomap: + clk_disable_unprepare(clk); +err_clk_enable: + clk_put(clk); +err_clk_get: + return ret; + +} + +static void __init mps2_timer_init(struct device_node *np) +{ + static int clksrc; + + if (!clksrc && !mps2_clocksource_init(np)) + clksrc = 1; + else + mps2_clockevents_init(np); +} + +CLOCKSOURCE_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init);