From patchwork Fri Nov 27 02:09:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 7710451 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 151DC9F2E9 for ; Fri, 27 Nov 2015 02:26:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 30A252056C for ; Fri, 27 Nov 2015 02:26:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4E65020561 for ; Fri, 27 Nov 2015 02:26:33 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a28iD-0007IB-4u; Fri, 27 Nov 2015 02:24:37 +0000 Received: from mail-pa0-f50.google.com ([209.85.220.50]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a28U4-0007Lh-37; Fri, 27 Nov 2015 02:10:07 +0000 Received: by pacdm15 with SMTP id dm15so99708143pac.3; Thu, 26 Nov 2015 18:09:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id; bh=B748DjIlbEoTnUoE7qye9Qa4FDQ25CYjsbfVIjGdaYA=; b=FZK3DCu5Je546wpZUe/2/A3DQ/Gi92fVs9ZWEjV+Dxvgv03r6OHuVjj4a+OeGOyNzk Geef7sJyjy0/cRKFJ4McyAFAdujDhWb7pGckzHQFIGMfFWC+ylCv0FyeHgBAJ46RHi+f 3+/SABSQEdW3hqbf9scnKfZOWfp80yS6szcRHpKzwG84vFZu9gB9hHXWSiM8jgG0fOQB LfaFb5nnoSup8vzdr2F08zeqvehtCcdFpT5ip4YjRpSAtk+P/JPc7fnIYEISLAPMqPVA jyH6D6g1MPYMd2sVXw9LkNEzsu387GhRyhq5uE42GSlV28VW5QtkIou2FbDLRB1d+EY9 wA2w== X-Received: by 10.98.13.218 with SMTP id 87mr43708951pfn.153.1448590178986; Thu, 26 Nov 2015 18:09:38 -0800 (PST) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id c20sm30069565pfd.17.2015.11.26.18.09.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Nov 2015 18:09:37 -0800 (PST) From: Chris Zhong To: dianders@chromium.org, heiko@sntech.de Subject: [PATCH v4] clk: rockchip: switch PLLs to slow mode before reboot for rk3288 Date: Fri, 27 Nov 2015 10:09:30 +0800 Message-Id: <1448590170-23776-1-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151126_181000_902222_5D259694 X-CRM114-Status: GOOD ( 12.86 ) X-Spam-Score: -2.2 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Chris Zhong , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We've been seeing some crashes at reboot test on rk3288-based systems, which boards have not reset pin connected to NPOR, they reboot by setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in a high frequency mode, some IPs might hang during soft reset. It appears that we can fix the problem by switching to slow mode before reboot, just like what we did before suspend. Signed-off-by: Chris Zhong Reviewed-by: Heiko Stuebner --- Changes in v4: - get rid of the CONFIG_PM_SLEEP conditionals completely Changes in v3: - remove include reboot.h Changes in v2: - replace restart_handlers with the shutdown callback of syscore drivers/clk/rockchip/clk-rk3288.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 9040878..97d314d 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -783,10 +783,10 @@ static const char *const rk3288_critical_clocks[] __initconst = { "pclk_pd_pmu", }; -#ifdef CONFIG_PM_SLEEP static void __iomem *rk3288_cru_base; -/* Some CRU registers will be reset in maskrom when the system +/* + * Some CRU registers will be reset in maskrom when the system * wakes up from fastboot. * So save them before suspend, restore them after resume. */ @@ -840,33 +840,28 @@ static void rk3288_clk_resume(void) } } +static void rk3288_clk_shutdown(void) +{ + writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON); +} + static struct syscore_ops rk3288_clk_syscore_ops = { .suspend = rk3288_clk_suspend, .resume = rk3288_clk_resume, + .shutdown = rk3288_clk_shutdown, }; -static void rk3288_clk_sleep_init(void __iomem *reg_base) -{ - rk3288_cru_base = reg_base; - register_syscore_ops(&rk3288_clk_syscore_ops); -} - -#else /* CONFIG_PM_SLEEP */ -static void rk3288_clk_sleep_init(void __iomem *reg_base) {} -#endif - static void __init rk3288_clk_init(struct device_node *np) { - void __iomem *reg_base; struct clk *clk; - reg_base = of_iomap(np, 0); - if (!reg_base) { + rk3288_cru_base = of_iomap(np, 0); + if (!rk3288_cru_base) { pr_err("%s: could not map cru region\n", __func__); return; } - rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS); /* xin12m is created by an cru-internal divider */ clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); @@ -907,10 +902,11 @@ static void __init rk3288_clk_init(struct device_node *np) &rk3288_cpuclk_data, rk3288_cpuclk_rates, ARRAY_SIZE(rk3288_cpuclk_rates)); - rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0), + rockchip_register_softrst(np, 12, + rk3288_cru_base + RK3288_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK); rockchip_register_restart_notifier(RK3288_GLB_SRST_FST); - rk3288_clk_sleep_init(reg_base); + register_syscore_ops(&rk3288_clk_syscore_ops); } CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);