From patchwork Wed Dec 2 17:22:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlo Caione X-Patchwork-Id: 7749791 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 96D559F350 for ; Wed, 2 Dec 2015 17:26:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CFBBF204A2 for ; Wed, 2 Dec 2015 17:26:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E1120204D2 for ; Wed, 2 Dec 2015 17:26:20 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4B8r-0005Ux-CK; Wed, 02 Dec 2015 17:24:33 +0000 Received: from mail-wm0-x235.google.com ([2a00:1450:400c:c09::235]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4B7a-0004Pq-Qw for linux-arm-kernel@lists.infradead.org; Wed, 02 Dec 2015 17:23:18 +0000 Received: by wmvv187 with SMTP id v187so265832939wmv.1 for ; Wed, 02 Dec 2015 09:22:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=T7xOHtvNONrpEtgDRqMZfxPb/Ux2IHpIRY8qtNqzz50=; b=PTuD7sKOtEdzHywCnMFAFvAFgciol6TxJCERgMhG4DEJ3WuLubiRs5cKOwfmt/9czt zY6KJjqYsDNNFkeYzQ3DNdGnwTr0TD5m8CZbQ/PAoPgMGSsI0uo3BIoOJJRYxPFxFa5P qiEm/Yv53E7fn14eVn7LDGOkIa3O4e1DGdDij3VADrGUXaj7newfoIhj9/SVl2kAcX6f CwWl3ZL43ilKymXhbRJ6o03LvtsHdeJiqSEaSYjSJQzrZjkgRG+yE+02KsWNAhugtG41 wmOfhSLIOc1Eo7Y43odPJHqy6Hk0vRtgZVsi3B4XopKN7+346oLTye6fWSN0PT2lgr8u d7pA== X-Received: by 10.28.68.213 with SMTP id r204mr44472842wma.35.1449076973534; Wed, 02 Dec 2015 09:22:53 -0800 (PST) Received: from localhost.localdomain ([212.91.95.170]) by smtp.gmail.com with ESMTPSA id s189sm4111113wmf.16.2015.12.02.09.22.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 02 Dec 2015 09:22:52 -0800 (PST) From: Carlo Caione To: robh+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, linux@arm.linux.org.uk, linux-meson@googlegroups.com, drake@endlessm.com, jerry.cao@amlogic.com, victor.wan@amlogic.com, pawel.moll@arm.com, arnd@arndb.de Subject: [PATCH v2 5/7] dt-bindings: Amlogic: Add SMP related documentation Date: Wed, 2 Dec 2015 18:22:31 +0100 Message-Id: <1449076953-5058-6-git-send-email-carlo@caione.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1449076953-5058-1-git-send-email-carlo@caione.org> References: <1449076953-5058-1-git-send-email-carlo@caione.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151202_092315_167186_4164A0AD X-CRM114-Status: GOOD ( 16.29 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Carlo Caione MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Carlo Caione With this patch we add documentation for: * power-management-unit: the PMU is used to bring up the cores during SMP operations * sram: among other things the sram is used to store the first code executed by the core when it is powered up * cpu-enable-method: the CPU enable method used by Amlogic Meson8b SoCs Signed-off-by: Carlo Caione Acked-by: Rob Herring --- .../devicetree/bindings/arm/amlogic/pmu.txt | 16 +++++++++++ .../devicetree/bindings/arm/amlogic/smp-sram.txt | 32 ++++++++++++++++++++++ Documentation/devicetree/bindings/arm/cpus.txt | 1 + 3 files changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt diff --git a/Documentation/devicetree/bindings/arm/amlogic/pmu.txt b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt new file mode 100644 index 0000000..7b9b2da --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/pmu.txt @@ -0,0 +1,16 @@ +Amlogic power-management-unit: +------------------------------- + +The pmu is used to turn off and on different power domains of the SoCs +This includes the power to the CPU cores. + +Required node properties: +- compatible value : = "amlogic,meson8b-pmu"; +- reg : physical base address and the size of the registers window + +Example: + + pmu@c81000e4 { + compatible = "amlogic,meson8b-pmu", "syscon"; + reg = <0xc81000e0 0x18>; + }; diff --git a/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt new file mode 100644 index 0000000..455ca20 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt @@ -0,0 +1,32 @@ +Amlogic SRAM for smp bringup: +------------------------------ + +Amlogic's smp-capable SoCs use part of the sram for the bringup of the cores. +Once the core gets powered up it executes the code that is residing at a +specific location. + +Therefore a reserved section sub-node has to be added to the mmio-sram +declaration. + +Required sub-node properties: +- compatible : should be "amlogic,meson8b-smp-sram" + +The rest of the properties should follow the generic mmio-sram discription +found in ../../misc/sram.txt + +Example: + + sram: sram@d9000000 { + compatible = "mmio-sram"; + reg = <0xd9000000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xd9000000 0x20000>; + + smp-sram@1ff80 { + compatible = "amlogic,meson8b-smp-sram"; + reg = <0x1ff80 0x8>; + }; + }; + + diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 3a07a87..22381b4 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -189,6 +189,7 @@ nodes to be present and contain the properties described below. can be one of: "allwinner,sun6i-a31" "allwinner,sun8i-a23" + "amlogic,meson8b-smp" "arm,psci" "brcm,brahma-b15" "marvell,armada-375-smp"