From patchwork Fri Dec 11 18:57:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dirk Behme X-Patchwork-Id: 7832251 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 741A09F1C2 for ; Fri, 11 Dec 2015 19:00:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 95FE820498 for ; Fri, 11 Dec 2015 19:00:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 43A29205BE for ; Fri, 11 Dec 2015 19:00:09 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a7StX-0002bW-T0; Fri, 11 Dec 2015 18:58:19 +0000 Received: from mail-wm0-x22c.google.com ([2a00:1450:400c:c09::22c]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a7StU-0002YE-KW for linux-arm-kernel@lists.infradead.org; Fri, 11 Dec 2015 18:58:17 +0000 Received: by mail-wm0-x22c.google.com with SMTP id c17so22528225wmd.1 for ; Fri, 11 Dec 2015 10:57:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=O2mDkkLA1Rv5o4sf96YW9jYbpQ/nFeUCeZYy/loM498=; b=Plq/l554OjhaNe7h9bHgyVNJd29Ezke5X3MPBS2KnDLMZva2Dx/B9hEcrZ0PplVN5s eupzTpPO1Z+frnJuLcgp7B84rnkHqwrmv1vmor4H/rsBUW+SEsST4fGjf3UJhTcEnH2y LlwncHz3881qzI0926jBy83SNnfAuhrh66U36N0+6suuUhczYhL1uFvgEGkC0aW8cvfJ p5xwxDFkDMwf05dWRixURgN2N3iiolhmSiwm5tleiEMNhU5y1I/fZMSU5al/xiehS1dG 7Ev7ZyRJ4lylKXIDz4A4YeAcjwtGrxaTQ1kD/Me/92WRGo/+DE6MY/FlVRR9LOPoXudM 4i2A== X-Received: by 10.194.236.38 with SMTP id ur6mr21526685wjc.13.1449860275075; Fri, 11 Dec 2015 10:57:55 -0800 (PST) Received: from localhost.localdomain (p4FEE272F.dip0.t-ipconnect.de. [79.238.39.47]) by smtp.gmail.com with ESMTPSA id an7sm18160985wjc.44.2015.12.11.10.57.53 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 11 Dec 2015 10:57:54 -0800 (PST) From: Dirk Behme To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] ARM: Documentation: l2x0: Mention separate controllers explicitly Date: Fri, 11 Dec 2015 19:57:47 +0100 Message-Id: <1449860267-16154-2-git-send-email-dirk.behme@gmail.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1449860267-16154-1-git-send-email-dirk.behme@gmail.com> References: <1449860267-16154-1-git-send-email-dirk.behme@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151211_105816_937351_3C3F0C0B X-CRM114-Status: GOOD ( 12.00 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Dirk Behme , sudeep.holla@arm.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The documentation in l2x0.txt is only valid for PL210/PL220/PL310 (and variants). Mention this explicitly. And add a note why this isn't valid for integrated L2 controllers. Signed-off-by: Dirk Behme --- Documentation/devicetree/bindings/arm/l2x0.txt | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/l2x0.txt b/Documentation/devicetree/bindings/arm/l2x0.txt index 06c88a4..aec5d02 100644 --- a/Documentation/devicetree/bindings/arm/l2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2x0.txt @@ -1,7 +1,8 @@ * ARM L2 Cache Controller -ARM cores often have a separate level 2 cache controller. There are various -implementations of the L2 cache controller with compatible programming models. +ARM cores often have a separate PL210/PL220/PL310 (and variants) based level 2 +cache controller. All these various implementations of the L2 cache controller +have compatible programming models (Note 1). Some of the properties that are just prefixed "cache-*" are taken from section 3.7.3 of the ePAPR v1.1 specification which can be found at: https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf @@ -91,3 +92,9 @@ L2: cache-controller { cache-level = <2>; interrupts = <45>; }; + +Note 1: The description in this document doesn't apply to integrated L2 + cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These + integrated L2 controllers are assumed to be all preconfigured by + early secure boot code. Thus no need to deal with their configuration + in the kernel at all.