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[79.238.45.249]) by smtp.gmail.com with ESMTPSA id 143sm10913027wmv.18.2015.12.13.01.15.22 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 13 Dec 2015 01:15:23 -0800 (PST) From: Dirk Behme To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2 v2] ARM: Documentation: l2c2x0: Mention separate controllers explicitly Date: Sun, 13 Dec 2015 10:15:17 +0100 Message-Id: <1449998117-5998-2-git-send-email-dirk.behme@gmail.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1449998117-5998-1-git-send-email-dirk.behme@gmail.com> References: <1449998117-5998-1-git-send-email-dirk.behme@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151213_011546_051103_D2818C24 X-CRM114-Status: GOOD ( 11.89 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, linux@arm.linux.org.uk, Dirk Behme , sudeep.holla@arm.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The documentation in l2c2x0.txt is only valid for L2C210/L2C220/L2C310 (also known as PL210/PL220/PL310 and variants). Mention this explicitly. And add a note why this isn't valid for integrated L2 controllers. Signed-off-by: Dirk Behme --- Changes in v2: Teplace the PL prefix with L2C Documentation/devicetree/bindings/arm/l2c2x0.txt | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt index 06c88a4..1c04354 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -1,7 +1,8 @@ * ARM L2 Cache Controller -ARM cores often have a separate level 2 cache controller. There are various -implementations of the L2 cache controller with compatible programming models. +ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/ +PL310 and variants) based level 2 cache controller. All these various implementations +of the L2 cache controller have compatible programming models (Note 1). Some of the properties that are just prefixed "cache-*" are taken from section 3.7.3 of the ePAPR v1.1 specification which can be found at: https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf @@ -91,3 +92,9 @@ L2: cache-controller { cache-level = <2>; interrupts = <45>; }; + +Note 1: The description in this document doesn't apply to integrated L2 + cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These + integrated L2 controllers are assumed to be all preconfigured by + early secure boot code. Thus no need to deal with their configuration + in the kernel at all.