From patchwork Mon Dec 14 13:27:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Kumar X-Patchwork-Id: 7844631 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D8CAABEEE1 for ; Mon, 14 Dec 2015 13:30:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E8D2F203C0 for ; Mon, 14 Dec 2015 13:30:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D637B201B4 for ; Mon, 14 Dec 2015 13:30:02 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a8TBJ-0000ZM-7Q; Mon, 14 Dec 2015 13:28:49 +0000 Received: from mail-gw1-out.broadcom.com ([216.31.210.62]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a8TB4-0000EY-U9 for linux-arm-kernel@lists.infradead.org; Mon, 14 Dec 2015 13:28:36 +0000 X-IronPort-AV: E=Sophos;i="5.20,427,1444719600"; d="scan'208";a="83370898" Received: from irvexchcas07.broadcom.com (HELO IRVEXCHCAS07.corp.ad.broadcom.com) ([10.9.208.55]) by mail-gw1-out.broadcom.com with ESMTP; 14 Dec 2015 07:52:08 -0800 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS07.corp.ad.broadcom.com (10.9.208.55) with Microsoft SMTP Server (TLS) id 14.3.235.1; Mon, 14 Dec 2015 05:28:14 -0800 Received: from mail-sj1-12.sj.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.3.235.1; Mon, 14 Dec 2015 05:28:15 -0800 Received: from lc-sj1-5011.broadcom.com (lc-sj1-5011.sj.broadcom.com [10.66.65.229]) by mail-sj1-12.sj.broadcom.com (Postfix) with ESMTP id 98E0B27A82; Mon, 14 Dec 2015 05:28:14 -0800 (PST) Received: by lc-sj1-5011.broadcom.com (Postfix, from userid 31394) id 9268B2011B5; Mon, 14 Dec 2015 05:28:14 -0800 (PST) From: Ashok Kumar To: , , , Subject: [RFC PATCH 2/2] arm64: Use PoU cache instr for I/D coherency Date: Mon, 14 Dec 2015 05:27:44 -0800 Message-ID: <1450099664-38554-3-git-send-email-ashoks@broadcom.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1450099664-38554-1-git-send-email-ashoks@broadcom.com> References: <1450099664-38554-1-git-send-email-ashoks@broadcom.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151214_052835_225742_86A2C879 X-CRM114-Status: GOOD ( 11.87 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ashok Kumar Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In systems with three levels of cache(PoU at L1 and PoC at L3), PoC cache flush instructions flushes L2 and L3 caches which could affect performance. For cache flushes for I and D coherency, PoU should suffice. So changing all I and D coherency related cache flushes to PoU. Introduced a new __flush_dcache_area_pou API for dcache flush till PoU Signed-off-by: Ashok Kumar --- arch/arm64/include/asm/cacheflush.h | 1 + arch/arm64/mm/cache.S | 22 ++++++++++++++++++++++ arch/arm64/mm/flush.c | 13 +++++++++---- 3 files changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index c75b8d0..e4b13f7 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -68,6 +68,7 @@ extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); extern void flush_icache_range(unsigned long start, unsigned long end); extern void __flush_dcache_area(void *addr, size_t len); +extern void __flush_dcache_area_pou(void *addr, size_t len); extern long __flush_cache_user_range(unsigned long start, unsigned long end); static inline void flush_cache_mm(struct mm_struct *mm) diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index eb48d5d..037293c 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -101,6 +101,28 @@ ENTRY(__flush_dcache_area) ENDPROC(__flush_dcache_area) /* + * __flush_dcache_area_pou(kaddr, size) + * + * Ensure that the data held in the page kaddr is written back to the + * page in question till Point of Unification. + * + * - kaddr - kernel address + * - size - size in question + */ +ENTRY(__flush_dcache_area_pou) + dcache_line_size x2, x3 + add x1, x0, x1 + sub x3, x2, #1 + bic x0, x0, x3 +1: dc cvau, x0 // clean D line till PoU + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret +ENDPROC(__flush_dcache_area_pou) + +/* * __inval_cache_range(start, end) * - start - start address of region * - end - end address of region diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index c26b804..6235af6 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -41,7 +41,7 @@ static void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, if (vma->vm_flags & VM_EXEC) { unsigned long addr = (unsigned long)kaddr; if (icache_is_aliasing()) { - __flush_dcache_area(kaddr, len); + __flush_dcache_area_pou(kaddr, len); __flush_icache_all(); } else { flush_icache_range(addr, addr + len); @@ -75,9 +75,14 @@ void __sync_icache_dcache(pte_t pte, unsigned long addr) return; if (!test_and_set_bit(PG_dcache_clean, &page->flags)) { - __flush_dcache_area(page_address(page), - PAGE_SIZE << compound_order(page)); - __flush_icache_all(); + if (icache_is_aliasing()) { + __flush_dcache_area_pou(page_address(page), + PAGE_SIZE << compound_order(page)); + __flush_icache_all(); + } else + flush_icache_range(page_address(page), + page_address(page) + + (PAGE_SIZE << compound_order(page))); } else if (icache_is_aivivt()) { __flush_icache_all(); }