From patchwork Mon Dec 14 16:31:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: pmallapp@broadcom.com X-Patchwork-Id: 7845871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E52DE9F3CD for ; Mon, 14 Dec 2015 16:33:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4779F203B4 for ; Mon, 14 Dec 2015 16:33:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9057020340 for ; Mon, 14 Dec 2015 16:33:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a8W1N-0008CZ-JP; Mon, 14 Dec 2015 16:30:45 +0000 Received: from mail-gw1-out.broadcom.com ([216.31.210.62]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a8W0v-0006np-Dl for linux-arm-kernel@lists.infradead.org; Mon, 14 Dec 2015 16:30:19 +0000 X-IronPort-AV: E=Sophos;i="5.20,427,1444719600"; d="scan'208";a="83395373" Received: from irvexchcas08.broadcom.com (HELO IRVEXCHCAS08.corp.ad.broadcom.com) ([10.9.208.57]) by mail-gw1-out.broadcom.com with ESMTP; 14 Dec 2015 10:53:53 -0800 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.3.235.1; Mon, 14 Dec 2015 08:29:56 -0800 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.3.235.1; Mon, 14 Dec 2015 08:29:56 -0800 Received: from lbblr-srv-cps-97.ban.broadcom.com (unknown [10.131.60.97]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 2920F40FE8; Mon, 14 Dec 2015 08:26:26 -0800 (PST) From: Prem Mallappa To: , , Subject: [PATCH] IOMMU: arm-smmu-v3: fix broken S2PS and AARCH64 in Broadcom Vulcan Date: Mon, 14 Dec 2015 22:01:27 +0530 Message-ID: <1450110687-32207-1-git-send-email-pmallapp@broadcom.com> X-Mailer: git-send-email 2.6.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151214_083017_811041_23A51569 X-CRM114-Status: GOOD ( 10.08 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jchandra@broadcom.com, Prem Mallappa Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Vulcan SMMUv3 looks for AARCH64 and S2PS inroder to validate the STE entry, which is a overkill, but when proper encoding not found; the SMMU stops processing PCIe read/write requests. Giving the h/w what it wants. Signed-off-by: Prem Mallappa --- drivers/iommu/arm-smmu-v3.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index d4af50d..dfda564 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -260,6 +260,7 @@ #define STRTAB_STE_2_S2VMID_MASK 0xffffUL #define STRTAB_STE_2_VTCR_SHIFT 32 #define STRTAB_STE_2_VTCR_MASK 0x7ffffUL +#define STRTAB_STE_2_S2PS_SHIFT 48 #define STRTAB_STE_2_S2AA64 (1UL << 51) #define STRTAB_STE_2_S2ENDI (1UL << 52) #define STRTAB_STE_2_S2PTW (1UL << 54) @@ -577,6 +578,7 @@ struct arm_smmu_device { u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_BROKEN_STE_VALID (1 << 1) u32 options; struct arm_smmu_cmdq cmdq; @@ -641,6 +643,7 @@ struct arm_smmu_option_prop { static struct arm_smmu_option_prop arm_smmu_options[] = { { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" }, + { ARM_SMMU_OPT_BROKEN_STE_VALID, "broadcom,broken-ste-valid-check" }, { 0, NULL}, }; @@ -1046,6 +1049,15 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, : STRTAB_STE_0_CFG_BYPASS; dst[0] = cpu_to_le64(val); dst[2] = 0; /* Nuke the VMID */ + + if (smmu && (smmu->options & ARM_SMMU_OPT_BROKEN_STE_VALID)) { +#define SMMU_STE_OAS_44_BITS 0x4UL + WARN_ON(smmu->oas != 44); + dst[1] = STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT; + dst[2] |= cpu_to_le64((SMMU_STE_OAS_44_BITS << STRTAB_STE_2_S2PS_SHIFT) | + STRTAB_STE_2_S2AA64); + } + if (ste_live) arm_smmu_sync_ste_for_sid(smmu, sid); return;