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[v2,2/8] irq: bcm2836: Add SMP support for the 2836

Message ID 1450310115-22163-3-git-send-email-eric@anholt.net (mailing list archive)
State New, archived
Headers show

Commit Message

Eric Anholt Dec. 16, 2015, 11:55 p.m. UTC 
From: Andrea Merello <andrea.merello@gmail.com>

The firmware sets the secondaries spinning waiting for a non-NULL
value to show up in the last IPI mailbox.

The original SMP port from the downstream tree was done by Andrea, and
Eric cleaned it up/rewrote it a few times from there.

Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/irqchip/irq-bcm2836.c | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

Comments

Baruch Siach Dec. 17, 2015, 5:17 a.m. UTC | #1 
Hi Eric,

On Wed, Dec 16, 2015 at 03:55:09PM -0800, Eric Anholt wrote:
> @@ -226,6 +228,26 @@ static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
>  	.xlate = irq_domain_xlate_onecell
>  };
>  
> +#ifdef CONFIG_SMP

Why not put this section under the existing '#ifdef CONFIG_SMP' just a few 
lines above?

> +int __init bcm2836_smp_boot_secondary(unsigned int cpu,
> +				      struct task_struct *idle)
> +{
> +	unsigned long secondary_startup_phys =
> +		(unsigned long)virt_to_phys((void *)secondary_startup);
> +
> +	dsb();
> +	writel(secondary_startup_phys,
> +	       intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
> +
> +	return 0;
> +}
> +
> +static const struct smp_operations bcm2836_smp_ops __initconst = {
> +	.smp_boot_secondary	= bcm2836_smp_boot_secondary,
> +};
> +
> +#endif

baruch
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Patch

diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c
index 6ec125e..c5ef4df 100644
--- a/drivers/irqchip/irq-bcm2836.c
+++ b/drivers/irqchip/irq-bcm2836.c
@@ -53,14 +53,16 @@ 
 /* Same status bits as above, but for FIQ. */
 #define LOCAL_FIQ_PENDING0		0x070
 /*
- * Mailbox0 write-to-set bits.  There are 16 mailboxes, 4 per CPU, and
+ * Mailbox write-to-set bits.  There are 16 mailboxes, 4 per CPU, and
  * these bits are organized by mailbox number and then CPU number.  We
  * use mailbox 0 for IPIs.  The mailbox's interrupt is raised while
  * any bit is set.
  */
 #define LOCAL_MAILBOX0_SET0		0x080
-/* Mailbox0 write-to-clear bits. */
+#define LOCAL_MAILBOX3_SET0		0x08c
+/* Mailbox write-to-clear bits. */
 #define LOCAL_MAILBOX0_CLR0		0x0c0
+#define LOCAL_MAILBOX3_CLR0		0x0cc
 
 #define LOCAL_IRQ_CNTPSIRQ	0
 #define LOCAL_IRQ_CNTPNSIRQ	1
@@ -226,6 +228,26 @@  static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
 	.xlate = irq_domain_xlate_onecell
 };
 
+#ifdef CONFIG_SMP
+int __init bcm2836_smp_boot_secondary(unsigned int cpu,
+				      struct task_struct *idle)
+{
+	unsigned long secondary_startup_phys =
+		(unsigned long)virt_to_phys((void *)secondary_startup);
+
+	dsb();
+	writel(secondary_startup_phys,
+	       intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
+
+	return 0;
+}
+
+static const struct smp_operations bcm2836_smp_ops __initconst = {
+	.smp_boot_secondary	= bcm2836_smp_boot_secondary,
+};
+
+#endif
+
 static void
 bcm2836_arm_irqchip_smp_init(void)
 {
@@ -237,6 +259,7 @@  bcm2836_arm_irqchip_smp_init(void)
 	register_cpu_notifier(&bcm2836_arm_irqchip_cpu_notifier);
 
 	set_smp_cross_call(bcm2836_arm_irqchip_send_ipi);
+	smp_set_ops(&bcm2836_smp_ops);
 #endif
 }