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Fri, 18 Dec 2015 16:01:50 +0000 Received: from mail-by2on0062.outbound.protection.outlook.com ([207.46.100.62] helo=na01-by2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a9xTW-0004HG-I3 for linux-arm-kernel@lists.infradead.org; Fri, 18 Dec 2015 16:01:47 +0000 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Yuri.Norov@caviumnetworks.com; Received: from localhost (95.143.213.121) by CO2PR07MB620.namprd07.prod.outlook.com (10.141.228.156) with Microsoft SMTP Server (TLS) id 15.1.337.19; Fri, 18 Dec 2015 16:01:23 +0000 From: Yury Norov To: , , Subject: [PATCH v4] arm64: run-time detection for aarch32 support Date: Fri, 18 Dec 2015 19:00:29 +0300 Message-ID: <1450454429-22976-1-git-send-email-ynorov@caviumnetworks.com> X-Mailer: git-send-email 2.5.0 MIME-Version: 1.0 X-Originating-IP: [95.143.213.121] X-ClientProxiedBy: VI1PR06CA0016.eurprd06.prod.outlook.com (25.162.116.154) To CO2PR07MB620.namprd07.prod.outlook.com (10.141.228.156) X-Microsoft-Exchange-Diagnostics: 1; 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X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ard.biesheuvel@linaro.org, will.deacon@arm.com, linux-kernel@vger.kernel.org, klimov.linux@gmail.com, Yury Norov , ddaney.cavm@gmail.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAD_ENC_HEADER,BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Kernel option COMPAT defines the ability of executing aarch32 binaries. Some platforms does not support aarch32 mode, and so cannot execute that binaries. But we cannot just disable COMPAT for them because the same kernel binary may be used by multiple platforms. In this patch, system_supports_aarch32_el0() is introduced to detect aarch32 support at run-time. v4: use new CPU Feature API. Signed-off-by: Yury Norov --- arch/arm64/include/asm/cpufeature.h | 7 +++++++ arch/arm64/include/asm/elf.h | 6 ++++-- arch/arm64/include/asm/sysreg.h | 1 + 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 8f271b8..781a2f7 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -184,6 +184,13 @@ static inline bool system_supports_mixed_endian_el0(void) return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1)); } +static inline bool system_supports_aarch32_el0(void) +{ + u64 pfr0 = read_system_reg(SYS_ID_AA64PFR0_EL1); + return ((pfr0 >> ID_AA64PFR0_EL0_SHIFT) & ID_AA64PFR0_ELx_MASK) + != ID_AA64PFR0_EL0_64BIT_ONLY; +} + #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h index faad6df..1053cd7 100644 --- a/arch/arm64/include/asm/elf.h +++ b/arch/arm64/include/asm/elf.h @@ -23,6 +23,7 @@ */ #include #include +#include typedef unsigned long elf_greg_t; @@ -173,8 +174,9 @@ typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG]; /* AArch32 EABI. */ #define EF_ARM_EABI_MASK 0xff000000 -#define compat_elf_check_arch(x) (((x)->e_machine == EM_ARM) && \ - ((x)->e_flags & EF_ARM_EABI_MASK)) +#define compat_elf_check_arch(x) (system_supports_aarch32_el0() \ + && ((x)->e_machine == EM_ARM) \ + && ((x)->e_flags & EF_ARM_EABI_MASK)) #define compat_start_thread compat_start_thread #define COMPAT_SET_PERSONALITY(ex) set_thread_flag(TIF_32BIT); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index d48ab5b..a67b203 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -102,6 +102,7 @@ #define ID_AA64PFR0_EL2_SHIFT 8 #define ID_AA64PFR0_EL1_SHIFT 4 #define ID_AA64PFR0_EL0_SHIFT 0 +#define ID_AA64PFR0_ELx_MASK 0xf #define ID_AA64PFR0_FP_NI 0xf #define ID_AA64PFR0_FP_SUPPORTED 0x0