From patchwork Thu Dec 24 01:42:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wang Nan X-Patchwork-Id: 7915031 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7284EBEEE5 for ; Thu, 24 Dec 2015 01:49:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3DDA520592 for ; Thu, 24 Dec 2015 01:49:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 20CA420591 for ; Thu, 24 Dec 2015 01:49:30 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aBv00-0004BM-E9; Thu, 24 Dec 2015 01:47:24 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aBuzv-00045Q-QF for linux-arm-kernel@lists.infradead.org; Thu, 24 Dec 2015 01:47:22 +0000 Received: from 172.24.1.48 (EHLO szxeml434-hub.china.huawei.com) ([172.24.1.48]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DBN01482; Thu, 24 Dec 2015 09:43:00 +0800 (CST) Received: from linux-4hy3.site (10.107.193.248) by szxeml434-hub.china.huawei.com (10.82.67.225) with Microsoft SMTP Server id 14.3.235.1; Thu, 24 Dec 2015 09:42:51 +0800 From: Wang Nan To: , , Subject: [PATCH v2] arm64: Store breakpoint single step state into pstate Date: Thu, 24 Dec 2015 01:42:42 +0000 Message-ID: <1450921362-198371-1-git-send-email-wangnan0@huawei.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1450860731-194418-1-git-send-email-wangnan0@huawei.com> References: <1450860731-194418-1-git-send-email-wangnan0@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.107.193.248] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0206.567B4DA5.0023, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 6bb11926dd8c5fbced531c1d331b3ff6 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151223_174720_558025_C20B59B6 X-CRM114-Status: GOOD ( 20.14 ) X-Spam-Score: -4.2 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Wang Nan , pi3orama@163.com, linux-kernel@vger.kernel.org, Jiri Olsa , Fengguang Wu , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Two 'perf test' fail on arm64: # perf test overflow 17: Test breakpoint overflow signal handler : FAILED! 18: Test breakpoint overflow sampling : FAILED! When breakpoint raises, after perf_bp_event, breakpoint_handler() temporary disables breakpoint and enables single step. Then in single_step_handler(), reenable breakpoint. Without doing this the breakpoint would be triggered again. However, if there's a pending signal and it have signal handler, control would be transfer to signal handler, so single step handler would be applied to the first instruction of signal handler. After the handler return, the instruction triggered the breakpoint would be executed again. At this time the breakpoint is enabled, so the breakpoint is triggered again. There was similar problem on x86, so we have following two commits: commit 24cda10996f5420ab962f91cd03c15869a3a94b1("x86/signals: Clear RF EFLAGS bit for signal handler"), commit 5e219b3c671b34b2d79468fe89c44c0460c0f02b("x86/signals: Propagate RF EFLAGS bit through the signal restore call"). When breakpoint handler enables single step, task is in a special state that, the breakpoint should be disabled, the single step should be enabled, and they should be toggled in single step handler. This state should be cleared when entering signal handler and restored after signal return like other program state. Considering the situation that signal raises inside signal handler, the only safe way to avoid the problem is to save this state into signal frame, like what x86 does. Different from x86 which has an RF EFLAGS bit to control debug behavior, there's no such bits on ARM64. Creating new fields in signal frame makes trouble because it is part of user API. Fortunately, on ARM64, we use a 64 bits pstate but the hardware only utilises the lowest 32 bits. The other 32 bits can be used by kernel to record this state. This patch create two bits in pstate to record the special state caused by breakpoint and watchpoint. In handle_signal, the state is checked and the bits are set accordingly, then the hardware is restored. When signal return, single step can be reenabled based on these bits. After this patch: # perf test overflow 17: Test breakpoint overflow signal handler : Ok 18: Test breakpoint overflow sampling : Ok Signed-off-by: Wang Nan Cc: AKASHI Takahiro Cc: Fengguang Wu Cc: Hanjun Guo Cc: Jiri Olsa Cc: Will Deacon --- v1 -> v2: Fix !CONFIG_HAVE_HW_BREAKPOINT build: add missing 'static inline'. arch/arm64/include/asm/debug-monitors.h | 9 ++++++ arch/arm64/include/uapi/asm/ptrace.h | 12 ++++++++ arch/arm64/kernel/hw_breakpoint.c | 50 +++++++++++++++++++++++++++++++++ arch/arm64/kernel/signal.c | 2 ++ 4 files changed, 73 insertions(+) diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h index 279c85b5..5529060 100644 --- a/arch/arm64/include/asm/debug-monitors.h +++ b/arch/arm64/include/asm/debug-monitors.h @@ -132,11 +132,20 @@ int kernel_active_single_step(void); #ifdef CONFIG_HAVE_HW_BREAKPOINT int reinstall_suspended_bps(struct pt_regs *regs); +u64 signal_toggle_single_step(void); +void signal_reinstall_single_step(u64 pstate); #else static inline int reinstall_suspended_bps(struct pt_regs *regs) { return -ENODEV; } +static inline u64 signal_toggle_single_step(void) +{ + return 0; +} +static inline void signal_reinstall_single_step(u64 pstate) +{ +} #endif int aarch32_break_handler(struct pt_regs *regs); diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h index 208db3d..bfb90f6 100644 --- a/arch/arm64/include/uapi/asm/ptrace.h +++ b/arch/arm64/include/uapi/asm/ptrace.h @@ -52,6 +52,18 @@ #define PSR_N_BIT 0x80000000 /* + * pstat in pt_regs and user_pt_regs are 64 bits. The highest 32 bits + * of it can be utilized by other. One user of them is signal handler. + */ +#define PSR_LINUX_MASK (0xffffffffUL << 32) +/* Single step and disable breakpoints */ +#define PSR_LINUX_HW_BP_SS (1UL << 32) +/* Single step and disable watchpoints */ +#define PSR_LINUX_HW_WP_SS (2UL << 32) + +#define PSR_LINUX_HW_SS (PSR_LINUX_HW_BP_SS | PSR_LINUX_HW_WP_SS) + +/* * Groups of PSR bits */ #define PSR_f 0xff000000 /* Flags */ diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c index b45c95d..e5a0998 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -954,3 +954,53 @@ int hw_breakpoint_exceptions_notify(struct notifier_block *unused, { return NOTIFY_DONE; } + +u64 signal_toggle_single_step(void) +{ + struct debug_info *debug_info = ¤t->thread.debug; + u64 retval = 0; + + if (likely(!debug_info->bps_disabled && !debug_info->wps_disabled)) + return 0; + + if (debug_info->bps_disabled) { + retval |= PSR_LINUX_HW_BP_SS; + toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 1); + debug_info->bps_disabled = 0; + } + + if (debug_info->wps_disabled) { + retval |= PSR_LINUX_HW_WP_SS; + toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1); + debug_info->wps_disabled = 0; + } + + if (debug_info->suspended_step) + debug_info->suspended_step = 0; + else + user_disable_single_step(current); + return retval; +} + +void signal_reinstall_single_step(u64 pstate) +{ + struct debug_info *debug_info = ¤t->thread.debug; + + if (likely(!(pstate & PSR_LINUX_HW_SS))) + return; + + if (pstate & PSR_LINUX_HW_BP_SS) { + debug_info->bps_disabled = 1; + toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 0); + } + + if (pstate & PSR_LINUX_HW_WP_SS) { + debug_info->wps_disabled = 1; + toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 0); + } + + if (test_thread_flag(TIF_SINGLESTEP)) + debug_info->suspended_step = 1; + else + user_enable_single_step(current); +} diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index e18c48c..1737710 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -151,6 +151,7 @@ asmlinkage long sys_rt_sigreturn(struct pt_regs *regs) if (restore_altstack(&frame->uc.uc_stack)) goto badframe; + signal_reinstall_single_step(regs->pstate); return regs->regs[0]; badframe: @@ -292,6 +293,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) int usig = ksig->sig; int ret; + regs->pstate |= signal_toggle_single_step(); /* * Set up the stack frame */