diff mbox

[v2,3/3] ARM64: dts: mt8173: Add CPU OPP, clock and regulator supply properties

Message ID 1451197318-12418-4-git-send-email-pi-cheng.chen@linaro.org (mailing list archive)
State New, archived
Headers show

Commit Message

pi-cheng.chen Dec. 27, 2015, 6:21 a.m. UTC
Add operating-points-v2, clock, and regulator supply properties
required by mt8173-cpufreq driver to enable it.

Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
---
This patch is based on the patch[1] that adds underlying clock MUX for
MT8173 which is needed by mt8173-cpufreq driver but not yet picked.

[1] http://article.gmane.org/gmane.linux.kernel.clk/325
---
 arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++++++
 arch/arm64/boot/dts/mediatek/mt8173.dtsi    | 90 +++++++++++++++++++++++++++++
 2 files changed, 108 insertions(+)

Comments

Viresh Kumar Dec. 28, 2015, 3:13 a.m. UTC | #1
On 27-12-15, 14:21, Pi-Cheng Chen wrote:
> Add operating-points-v2, clock, and regulator supply properties
> required by mt8173-cpufreq driver to enable it.
> 
> Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
> ---
> This patch is based on the patch[1] that adds underlying clock MUX for
> MT8173 which is needed by mt8173-cpufreq driver but not yet picked.
> 
> [1] http://article.gmane.org/gmane.linux.kernel.clk/325
> ---
>  arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++++++
>  arch/arm64/boot/dts/mediatek/mt8173.dtsi    | 90 +++++++++++++++++++++++++++++
>  2 files changed, 108 insertions(+)

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Arnd Bergmann Jan. 5, 2016, 10:21 a.m. UTC | #2
On Monday 28 December 2015 08:43:40 Viresh Kumar wrote:
> On 27-12-15, 14:21, Pi-Cheng Chen wrote:
> > Add operating-points-v2, clock, and regulator supply properties
> > required by mt8173-cpufreq driver to enable it.
> > 
> > Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
> > ---
> > This patch is based on the patch[1] that adds underlying clock MUX for
> > MT8173 which is needed by mt8173-cpufreq driver but not yet picked.
> > 
> > [1] http://article.gmane.org/gmane.linux.kernel.clk/325
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++++++
> >  arch/arm64/boot/dts/mediatek/mt8173.dtsi    | 90 +++++++++++++++++++++++++++++
> >  2 files changed, 108 insertions(+)
> 
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> 

This patch is now in linux-next through Rafael's pm tree, and it breaks the
arm64 build:

        arm64-defconfig
Error: ../arch/arm64/boot/dts/mediatek/mt8173.dtsi:132.24-25 syntax error


Please revert.

In the future, please send all dts changes through the proper maintainer
channels (-> Mattias -> arm-soc), and make sure they actually build.

	Arnd
Viresh Kumar Jan. 5, 2016, 10:24 a.m. UTC | #3
On 05-01-16, 11:21, Arnd Bergmann wrote:
> On Monday 28 December 2015 08:43:40 Viresh Kumar wrote:
> > On 27-12-15, 14:21, Pi-Cheng Chen wrote:
> > > Add operating-points-v2, clock, and regulator supply properties
> > > required by mt8173-cpufreq driver to enable it.
> > > 
> > > Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
> > > ---
> > > This patch is based on the patch[1] that adds underlying clock MUX for
> > > MT8173 which is needed by mt8173-cpufreq driver but not yet picked.
> > > 
> > > [1] http://article.gmane.org/gmane.linux.kernel.clk/325
> > > ---
> > >  arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++++++
> > >  arch/arm64/boot/dts/mediatek/mt8173.dtsi    | 90 +++++++++++++++++++++++++++++
> > >  2 files changed, 108 insertions(+)
> > 
> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> > 
> 
> This patch is now in linux-next through Rafael's pm tree, and it breaks the
> arm64 build:
> 
>         arm64-defconfig
> Error: ../arch/arm64/boot/dts/mediatek/mt8173.dtsi:132.24-25 syntax error
> 
> 
> Please revert.
> 
> In the future, please send all dts changes through the proper maintainer
> channels (-> Mattias -> arm-soc), and make sure they actually build.

Rafael has already reverted that, AFAIK, after Mark Brown reported the
build issue.
Matthias Brugger Feb. 2, 2016, 11:06 a.m. UTC | #4
On 05/01/16 11:24, Viresh Kumar wrote:
> On 05-01-16, 11:21, Arnd Bergmann wrote:
>> On Monday 28 December 2015 08:43:40 Viresh Kumar wrote:
>>> On 27-12-15, 14:21, Pi-Cheng Chen wrote:
>>>> Add operating-points-v2, clock, and regulator supply properties
>>>> required by mt8173-cpufreq driver to enable it.
>>>>
>>>> Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
>>>> ---
>>>> This patch is based on the patch[1] that adds underlying clock MUX for
>>>> MT8173 which is needed by mt8173-cpufreq driver but not yet picked.
>>>>
>>>> [1] http://article.gmane.org/gmane.linux.kernel.clk/325
>>>> ---
>>>>   arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++++++
>>>>   arch/arm64/boot/dts/mediatek/mt8173.dtsi    | 90 +++++++++++++++++++++++++++++
>>>>   2 files changed, 108 insertions(+)
>>>
>>> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
>>>
>>
>> This patch is now in linux-next through Rafael's pm tree, and it breaks the
>> arm64 build:
>>
>>          arm64-defconfig
>> Error: ../arch/arm64/boot/dts/mediatek/mt8173.dtsi:132.24-25 syntax error
>>
>>
>> Please revert.
>>
>> In the future, please send all dts changes through the proper maintainer
>> channels (-> Mattias -> arm-soc), and make sure they actually build.
>
> Rafael has already reverted that, AFAIK, after Mark Brown reported the
> build issue.
>

Applied to v4.5-next/dts

Thanks.
Matthias Brugger Feb. 2, 2016, 2:09 p.m. UTC | #5
On 02/02/16 12:06, Matthias Brugger wrote:
>
>
> On 05/01/16 11:24, Viresh Kumar wrote:
>> On 05-01-16, 11:21, Arnd Bergmann wrote:
>>> On Monday 28 December 2015 08:43:40 Viresh Kumar wrote:
>>>> On 27-12-15, 14:21, Pi-Cheng Chen wrote:
>>>>> Add operating-points-v2, clock, and regulator supply properties
>>>>> required by mt8173-cpufreq driver to enable it.
>>>>>
>>>>> Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
>>>>> ---
>>>>> This patch is based on the patch[1] that adds underlying clock MUX for
>>>>> MT8173 which is needed by mt8173-cpufreq driver but not yet picked.
>>>>>
>>>>> [1] http://article.gmane.org/gmane.linux.kernel.clk/325
>>>>> ---
>>>>>   arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++++++
>>>>>   arch/arm64/boot/dts/mediatek/mt8173.dtsi    | 90
>>>>> +++++++++++++++++++++++++++++
>>>>>   2 files changed, 108 insertions(+)
>>>>
>>>> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
>>>>
>>>
>>> This patch is now in linux-next through Rafael's pm tree, and it
>>> breaks the
>>> arm64 build:
>>>
>>>          arm64-defconfig
>>> Error: ../arch/arm64/boot/dts/mediatek/mt8173.dtsi:132.24-25 syntax
>>> error
>>>
>>>
>>> Please revert.
>>>
>>> In the future, please send all dts changes through the proper maintainer
>>> channels (-> Mattias -> arm-soc), and make sure they actually build.
>>
>> Rafael has already reverted that, AFAIK, after Mark Brown reported the
>> build issue.
>>
>
> Applied to v4.5-next/dts
>

I oversaw that this needs a clock patch, which is not yet mainlined.
I deleted this patch from my tree.
pi-cheng.chen Feb. 3, 2016, 1:46 a.m. UTC | #6
On Tue, Feb 2, 2016 at 10:09 PM, Matthias Brugger
<matthias.bgg@gmail.com> wrote:
>
>
> On 02/02/16 12:06, Matthias Brugger wrote:
>>
>>
>>
>> On 05/01/16 11:24, Viresh Kumar wrote:
>>>
>>> On 05-01-16, 11:21, Arnd Bergmann wrote:
>>>>
>>>> On Monday 28 December 2015 08:43:40 Viresh Kumar wrote:
>>>>>
>>>>> On 27-12-15, 14:21, Pi-Cheng Chen wrote:
>>>>>>
>>>>>> Add operating-points-v2, clock, and regulator supply properties
>>>>>> required by mt8173-cpufreq driver to enable it.
>>>>>>
>>>>>> Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
>>>>>> ---
>>>>>> This patch is based on the patch[1] that adds underlying clock MUX for
>>>>>> MT8173 which is needed by mt8173-cpufreq driver but not yet picked.
>>>>>>
>>>>>> [1] http://article.gmane.org/gmane.linux.kernel.clk/325
>>>>>> ---
>>>>>>   arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++++++
>>>>>>   arch/arm64/boot/dts/mediatek/mt8173.dtsi    | 90
>>>>>> +++++++++++++++++++++++++++++
>>>>>>   2 files changed, 108 insertions(+)
>>>>>
>>>>>
>>>>> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
>>>>>
>>>>
>>>> This patch is now in linux-next through Rafael's pm tree, and it
>>>> breaks the
>>>> arm64 build:
>>>>
>>>>          arm64-defconfig
>>>> Error: ../arch/arm64/boot/dts/mediatek/mt8173.dtsi:132.24-25 syntax
>>>> error
>>>>
>>>>
>>>> Please revert.
>>>>
>>>> In the future, please send all dts changes through the proper maintainer
>>>> channels (-> Mattias -> arm-soc), and make sure they actually build.
>>>
>>>
>>> Rafael has already reverted that, AFAIK, after Mark Brown reported the
>>> build issue.
>>>
>>
>> Applied to v4.5-next/dts
>>
>
> I oversaw that this needs a clock patch, which is not yet mainlined.
> I deleted this patch from my tree.

I should mention that explicitly.
Sorry for the inconvenience.

Pi-Cheng
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 811cb76..5b6321b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -405,6 +405,24 @@ 
 	status = "okay";
 };
 
+&cpu0 {
+	proc-supply = <&mt6397_vpca15_reg>;
+};
+
+&cpu1 {
+	proc-supply = <&mt6397_vpca15_reg>;
+};
+
+&cpu2 {
+	proc-supply = <&da9211_vcpu_reg>;
+	sram-supply = <&mt6397_vsramca7_reg>;
+};
+
+&cpu3 {
+	proc-supply = <&da9211_vcpu_reg>;
+	sram-supply = <&mt6397_vsramca7_reg>;
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 4dd5f93..ae28c12 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -24,6 +24,80 @@ 
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	cluster0_opp: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp@507000000 {
+			opp-hz = /bits/ 64 <507000000>;
+			opp-microvolt = <859000>;
+		};
+		opp@702000000 {
+			opp-hz = /bits/ 64 <702000000>;
+			opp-microvolt = <908000>;
+		};
+		opp@1001000000 {
+			opp-hz = /bits/ 64 <1001000000>;
+			opp-microvolt = <983000>;
+		};
+		opp@1105000000 {
+			opp-hz = /bits/ 64 <1105000000>;
+			opp-microvolt = <1009000>;
+		};
+		opp@1183000000 {
+			opp-hz = /bits/ 64 <1183000000>;
+			opp-microvolt = <1028000>;
+		};
+		opp@1404000000 {
+			opp-hz = /bits/ 64 <1404000000>;
+			opp-microvolt = <1083000>;
+		};
+		opp@1508000000 {
+			opp-hz = /bits/ 64 <1508000000>;
+			opp-microvolt = <1109000>;
+		};
+		opp@1573000000 {
+			opp-hz = /bits/ 64 <1573000000>;
+			opp-microvolt = <1125000>;
+		};
+	};
+
+	cluster1_opp: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp@507000000 {
+			opp-hz = /bits/ 64 <507000000>;
+			opp-microvolt = <828000>;
+		};
+		opp@702000000 {
+			opp-hz = /bits/ 64 <702000000>;
+			opp-microvolt = <867000>;
+		};
+		opp@1001000000 {
+			opp-hz = /bits/ 64 <1001000000>;
+			opp-microvolt = <927000>;
+		};
+		opp@1209000000 {
+			opp-hz = /bits/ 64 <1209000000>;
+			opp-microvolt = <968000>;
+		};
+		opp@1404000000 {
+			opp-hz = /bits/ 64 <1404000000>;
+			opp-microvolt = <1007000>;
+		};
+		opp@1612000000 {
+			opp-hz = /bits/ 64 <1612000000>;
+			opp-microvolt = <1049000>;
+		};
+		opp@1807000000 {
+			opp-hz = /bits/ 64 <1807000000>;
+			opp-microvolt = <1089000>;
+		};
+		opp@1989000000 {
+			opp-hz = /bits/ 64 <1989000000>;
+			opp-microvolt = <1125000>;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -54,6 +128,10 @@ 
 			reg = <0x000>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&infracfg CLK_INFRA_CA53SEL>,
+				 <&apmixedsys CLK_APMIXED_MAINPLL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu1: cpu@1 {
@@ -62,6 +140,10 @@ 
 			reg = <0x001>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&infracfg CLK_INFRA_CA53SEL>,
+				 <&apmixedsys CLK_APMIXED_MAINPLL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu2: cpu@100 {
@@ -70,6 +152,10 @@ 
 			reg = <0x100>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&infracfg CLK_INFRA_CA57SEL>,
+				 <&apmixedsys CLK_APMIXED_MAINPLL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster1_opp>;
 		};
 
 		cpu3: cpu@101 {
@@ -78,6 +164,10 @@ 
 			reg = <0x101>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&infracfg CLK_INFRA_CA57SEL>,
+				 <&apmixedsys CLK_APMIXED_MAINPLL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster1_opp>;
 		};
 
 		idle-states {