From patchwork Sun Dec 27 06:21:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "pi-cheng.chen" X-Patchwork-Id: 7923011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7AA6BBEEE5 for ; Sun, 27 Dec 2015 06:26:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 50B57202F2 for ; Sun, 27 Dec 2015 06:26:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 544C6202E6 for ; Sun, 27 Dec 2015 06:26:09 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aD4jT-0004FH-P2; Sun, 27 Dec 2015 06:23:07 +0000 Received: from mail-pf0-x22c.google.com ([2607:f8b0:400e:c00::22c]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aD4j1-00046q-IK for linux-arm-kernel@lists.infradead.org; Sun, 27 Dec 2015 06:22:41 +0000 Received: by mail-pf0-x22c.google.com with SMTP id e65so45093111pfe.1 for ; Sat, 26 Dec 2015 22:22:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XeBvzwrD0k26A3GAc/Eh0kSpf9pNbNJNemUMsrBbv5Q=; b=QAByK1oEVLdff0fKX3sbFsDTRKEgowOB57Cp8GzY7VF1wFgKfSDZhCnigaFpf/O4/v 6AU+DY3QcThsr+R/v2NIhodMnNbzwKniG8peuXPOBidRh+p7ACchWSipyWh+b3sb6O01 +GU2hQxWdH6DSsk2tvUXPqturbcPBM2hl9QF8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XeBvzwrD0k26A3GAc/Eh0kSpf9pNbNJNemUMsrBbv5Q=; b=PYCw7akxVd6LoHMO9I0+b+sb3HfNyNE5R5TjlQaMPIPV0vDB64Z+qKEtTbY2/hA5QI RB6gD2JJKcTmISpElABrFXIj1azMmYFWfMEUb0RTggYcMt/swPQCsys1ZWPfURzwtJ6d /P6ZjH6ort0FOaRsTgmeCPoVhlcky+Mg/QBxDlbGx+ZuFVgIMALsyj09vYHkEwHRxZe8 f5L09RykVTiiW1Bc/5KsS0l2dsFNhl99uaIXhcwVQqNTBxzZaew40MFXS0N97pTsqoTb AigQp+XgSSZdXF7rZUPZk9pWtyqD6IcshFVh82zg18Vee0mciSmTUDY78AbgOLTJIPMh fIkw== X-Gm-Message-State: ALoCoQm8YHB7ATg09ewZANoc0fnE7j5e/vXqfPrZnVNsjMxvWBn5dPak2FJvto2LnOmj41BrLUNRaLjlP2j9HXe0vo+7fWEtgg== X-Received: by 10.98.73.7 with SMTP id w7mr69201332pfa.158.1451197338911; Sat, 26 Dec 2015 22:22:18 -0800 (PST) Received: from localhost.localdomain ([124.219.30.17]) by smtp.googlemail.com with ESMTPSA id tu9sm73508609pac.0.2015.12.26.22.22.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 26 Dec 2015 22:22:18 -0800 (PST) From: Pi-Cheng Chen To: Viresh Kumar , Matthias Brugger Subject: [PATCH v2 3/3] ARM64: dts: mt8173: Add CPU OPP, clock and regulator supply properties Date: Sun, 27 Dec 2015 14:21:58 +0800 Message-Id: <1451197318-12418-4-git-send-email-pi-cheng.chen@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1451197318-12418-1-git-send-email-pi-cheng.chen@linaro.org> References: <1451197318-12418-1-git-send-email-pi-cheng.chen@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151226_222239_800177_060F41B7 X-CRM114-Status: GOOD ( 11.02 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linaro-kernel@lists.linaro.org, linux-pm@vger.kernel.org, Michael Turquette , Daniel Kurtz , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add operating-points-v2, clock, and regulator supply properties required by mt8173-cpufreq driver to enable it. Signed-off-by: Pi-Cheng Chen Acked-by: Viresh Kumar --- This patch is based on the patch[1] that adds underlying clock MUX for MT8173 which is needed by mt8173-cpufreq driver but not yet picked. [1] http://article.gmane.org/gmane.linux.kernel.clk/325 --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 ++++++ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 90 +++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 811cb76..5b6321b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -405,6 +405,24 @@ status = "okay"; }; +&cpu0 { + proc-supply = <&mt6397_vpca15_reg>; +}; + +&cpu1 { + proc-supply = <&mt6397_vpca15_reg>; +}; + +&cpu2 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; + +&cpu3 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 4dd5f93..ae28c12 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -24,6 +24,80 @@ #address-cells = <2>; #size-cells = <2>; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp@507000000 { + opp-hz = /bits/ 64 <507000000>; + opp-microvolt = <859000>; + }; + opp@702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-microvolt = <908000>; + }; + opp@1001000000 { + opp-hz = /bits/ 64 <1001000000>; + opp-microvolt = <983000>; + }; + opp@1105000000 { + opp-hz = /bits/ 64 <1105000000>; + opp-microvolt = <1009000>; + }; + opp@1183000000 { + opp-hz = /bits/ 64 <1183000000>; + opp-microvolt = <1028000>; + }; + opp@1404000000 { + opp-hz = /bits/ 64 <1404000000>; + opp-microvolt = <1083000>; + }; + opp@1508000000 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <1109000>; + }; + opp@1573000000 { + opp-hz = /bits/ 64 <1573000000>; + opp-microvolt = <1125000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + opp@507000000 { + opp-hz = /bits/ 64 <507000000>; + opp-microvolt = <828000>; + }; + opp@702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-microvolt = <867000>; + }; + opp@1001000000 { + opp-hz = /bits/ 64 <1001000000>; + opp-microvolt = <927000>; + }; + opp@1209000000 { + opp-hz = /bits/ 64 <1209000000>; + opp-microvolt = <968000>; + }; + opp@1404000000 { + opp-hz = /bits/ 64 <1404000000>; + opp-microvolt = <1007000>; + }; + opp@1612000000 { + opp-hz = /bits/ 64 <1612000000>; + opp-microvolt = <1049000>; + }; + opp@1807000000 { + opp-hz = /bits/ 64 <1807000000>; + opp-microvolt = <1089000>; + }; + opp@1989000000 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1125000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -54,6 +128,10 @@ reg = <0x000>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { @@ -62,6 +140,10 @@ reg = <0x001>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@100 { @@ -70,6 +152,10 @@ reg = <0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA57SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; }; cpu3: cpu@101 { @@ -78,6 +164,10 @@ reg = <0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&infracfg CLK_INFRA_CA57SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; }; idle-states {