From patchwork Mon Jan 4 11:54:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 7947501 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 36419BEEE5 for ; Mon, 4 Jan 2016 11:59:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 35F582013A for ; Mon, 4 Jan 2016 11:59:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 106302035B for ; Mon, 4 Jan 2016 11:59:51 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aG3mA-00071W-V3; Mon, 04 Jan 2016 11:58:15 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aG3jk-0004LN-U5 for linux-arm-kernel@lists.infradead.org; Mon, 04 Jan 2016 11:55:51 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B177D5F7; Mon, 4 Jan 2016 03:54:44 -0800 (PST) Received: from e106634-lin.cambridge.arm.com (e106634-lin.cambridge.arm.com [10.1.209.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5CE0A3F24D; Mon, 4 Jan 2016 03:55:15 -0800 (PST) From: "Suzuki K. Poulose" To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 09/11] arm-cci: CCI-500: Work around PMU counter writes Date: Mon, 4 Jan 2016 11:54:48 +0000 Message-Id: <1451908490-2615-10-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1451908490-2615-1-git-send-email-suzuki.poulose@arm.com> References: <1451908490-2615-1-git-send-email-suzuki.poulose@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160104_035545_357964_65F70442 X-CRM114-Status: GOOD ( 15.66 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, "Suzuki K. Poulose" , peterz@infradead.org, punit.agrawal@arm.com, linux-kernel@vger.kernel.org, arm@kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The CCI PMU driver sets the event counter to the half of the maximum value(2^31) it can count before we start the counters via pmu_event_set_period(). This is done to give us the best chance to handle the overflow interrupt, taking care of extreme interrupt latencies. However, CCI-500 comes with advanced power saving schemes, which disables the clock to the event counters unless the counters are enabled to count (PMCR.CEN). This prevents the driver from writing the period to the counters before starting them. Also, there is no way we can reset the individual event counter to 0 (PMCR.RST resets all the counters, losing their current readings). However the value of the counter is preserved and could be read back, when the counters are not enabled. So we cannot reliably use the counters and compute the number of events generated during the sampling period since we don't have the value of the counter at start. This patch works around this issue by changing writes to the counter with the following steps. 1) Disable all the counters (remembering any counters which were enabled) 2) Enable the PMU, now that all the counters are disabled. For each counter to be programmed, repeat steps 3-7 3) Save the current event and program the target counter to count an invalid event, which by spec is guaranteed to not-generate any events. 4) Enable the target counter. 5) Write to the target counter. 6) Disable the target counter 7) Restore the event back on the target counter. 8) Disable the PMU 9) Restore the status of the all the counters Cc: Punit Agrawal Cc: Mark Rutland Signed-off-by: Suzuki K. Poulose --- drivers/bus/arm-cci.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c index 47c9581..cb2b468 100644 --- a/drivers/bus/arm-cci.c +++ b/drivers/bus/arm-cci.c @@ -837,6 +837,68 @@ static void __pmu_write_counter(struct cci_pmu *cci_pmu, u32 value, int idx) pmu_write_register(cci_pmu, value, idx, CCI_PMU_CNTR); } +#ifdef CONFIG_ARM_CCI500_PMU + +/* + * CCI-500 has advanced power saving policies, which could gate the + * clocks to the PMU counters, which makes the writes to them ineffective. + * The only way to write to those counters is when the global counters + * are enabled and the particular counter is enabled. + * + * So we do the following : + * + * 1) Disable all the PMU counters, saving their current state + * 2) Enable the global PMU profiling, now that all counters are + * disabled. + * + * For each counter to be programmed, repeat steps 3-7: + * + * 3) Write an invalid event code to the event control register for the + counter, so that the counters are not modified. + * 4) Enable the counter control for the counter. + * 5) Set the counter value + * 6) Restore the event in the target counter + * 7) Disable the counter + * + * 8) Disable the global PMU. + * 9) Restore the status of the rest of the counters. + * + * We choose an event code which has very little chances of getting + * assigned a valid code for step(2). We use the highest possible + * event code (0x1f) for the master interface 0. + */ +#define CCI500_INVALID_EVENT ((CCI500_PORT_M0 << CCI500_PMU_EVENT_SOURCE_SHIFT) | \ + (CCI500_PMU_EVENT_CODE_MASK << CCI500_PMU_EVENT_CODE_SHIFT)) +static void cci500_pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask, u32 value) +{ + int i; + unsigned long saved_mask[BITS_TO_LONGS(cci_pmu->num_cntrs)]; + + memset(saved_mask, 0, + BITS_TO_LONGS(cci_pmu->num_cntrs) * sizeof(unsigned long)); + + pmu_save_counters(cci_pmu, saved_mask); + + /* Now that all the counters are disabled, we can safely turn the PMU on */ + __cci_pmu_enable(); + + for_each_set_bit(i, mask, cci_pmu->num_cntrs) { + u32 event = cci_pmu->hw_events.events[i]->hw.config_base; + + pmu_set_event(cci_pmu, i, CCI500_INVALID_EVENT); + pmu_enable_counter(cci_pmu, i); + __pmu_write_counter(cci_pmu, value, i); + pmu_disable_counter(cci_pmu, i); + pmu_set_event(cci_pmu, i, event); + } + + __cci_pmu_disable(); + + pmu_restore_counters(cci_pmu, saved_mask); +} + +#endif /* CONFIG_ARM_CCI500_PMU */ + static void pmu_write_counter(struct perf_event *event, u32 value) { struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); @@ -1478,6 +1540,7 @@ static struct cci_pmu_model cci_pmu_models[] = { }, }, .validate_hw_event = cci500_validate_hw_event, + .write_counters = cci500_pmu_write_counters, }, #endif };