From patchwork Thu Jan 14 21:46:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 8035961 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BC750BEEE5 for ; Thu, 14 Jan 2016 21:53:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D2DBE20390 for ; Thu, 14 Jan 2016 21:53:49 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 096042035D for ; Thu, 14 Jan 2016 21:53:49 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aJpoV-0001BZ-WC; Thu, 14 Jan 2016 21:52:16 +0000 Received: from mail-pa0-x236.google.com ([2607:f8b0:400e:c03::236]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aJpk1-0004MU-16 for linux-arm-kernel@lists.infradead.org; Thu, 14 Jan 2016 21:47:41 +0000 Received: by mail-pa0-x236.google.com with SMTP id yy13so290501688pab.3 for ; Thu, 14 Jan 2016 13:47:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+pjQ/jgjXxPYO2fxZeddVphbXZ3K4GystY86lOz1oPk=; b=AbXa92hNnIf747bcA3/I+MOVfesHXdkotrlj16iQSfijcRqy7+4Q8nV8Xbn99CWkTN 8V6S7wWnj2kTWQRVH05MciZPEZSX7KxCup6UPtkWzLo6DmeZHop9UH2uCnMPcrtzMzUl vsP2uB647lTOJsz4dkI7tNPO6fiYpII7m1Aks= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+pjQ/jgjXxPYO2fxZeddVphbXZ3K4GystY86lOz1oPk=; b=C2Lu3AnsMKhA+xWQ27uxWIEy51DVdhsKKo+6Tku1SkCOzd3WpyD1gJDbkufhGp2ow4 NZNeSdEq6MZCw+UHRa2ztq6X7tKEWWOfLE2/X13aXEsQVAuOgIPcG3qAny1KybC9Km+a 6toGKyud4BKw7v52wEmNt6Dj9PrloVerJIn/tpPmOheW0NF49fT5womy89e9wkLMS/81 CaSqdx81i6YHUtt7mXHRIGlcKzI00aQX7LtIvFBohytB7ud8jSGY6/ujMEQk9PbcunTq NAr+NJUz++rKyeBgBOuSvOiNfTWERs+dLxt/pLa/jf30pY15E+LfALtoRwz2aAYtGd3n fz+Q== X-Gm-Message-State: ALoCoQn3hOZCeh4SbhpbgK0RQDXj0G1D/kyVOTDVdDgu3Pe9+ItEojyu29MXG6gazAkPIqERYJCGrrS6DlFr4eRTC7b0KolO2A== X-Received: by 10.66.55.66 with SMTP id q2mr9559394pap.120.1452808038429; Thu, 14 Jan 2016 13:47:18 -0800 (PST) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id c87sm11383309pfj.41.2016.01.14.13.47.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jan 2016 13:47:17 -0800 (PST) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V8 11/23] coresight: etm3x: consolidating initial config Date: Thu, 14 Jan 2016 14:46:05 -0700 Message-Id: <1452807977-8069-12-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1452807977-8069-1-git-send-email-mathieu.poirier@linaro.org> References: <1452807977-8069-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160114_134737_459358_53952FE3 X-CRM114-Status: GOOD ( 11.89 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, Mathieu Poirier , linux-doc@vger.kernel.org, zhang.chunyan@linaro.org, rabin@rab.in, mike.leach@arm.com, tor@ti.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There is really no point in having two functions to take care of doing the initial tracer configuration. As such moving everything to 'etm_set_default()'. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm3x.c | 37 ++++++++++----------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 6469d7a83aa1..d0f2a55f9b16 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -41,7 +41,6 @@ module_param_named(boot_enable, boot_enable, int, S_IRUGO); /* The number of ETM/PTM currently registered */ static int etm_count; static struct etm_drvdata *etmdrvdata[NR_CPUS]; -static void etm_init_default_data(struct etm_config *config); /* * Memory mapped writes to clear os lock are not supported on some processors @@ -194,6 +193,19 @@ void etm_set_default(struct etm_config *config) if (WARN_ON_ONCE(!config)) return; + /* + * Taken verbatim from the TRM: + * + * To trace all memory: + * set bit [24] in register 0x009, the ETMTECR1, to 1 + * set all other bits in register 0x009, the ETMTECR1, to 0 + * set all bits in register 0x007, the ETMTECR2, to 0 + * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). + */ + config->enable_ctrl1 = BIT(24); + config->enable_ctrl2 = 0x0; + config->enable_event = ETM_HARD_WIRE_RES_A; + config->trigger_event = ETM_DEFAULT_EVENT_VAL; config->enable_event = ETM_HARD_WIRE_RES_A; @@ -577,27 +589,6 @@ static void etm_init_arch_data(void *info) CS_LOCK(drvdata->base); } -static void etm_init_default_data(struct etm_config *config) -{ - if (WARN_ON_ONCE(!config)) - return; - - etm_set_default(config); - - /* - * Taken verbatim from the TRM: - * - * To trace all memory: - * set bit [24] in register 0x009, the ETMTECR1, to 1 - * set all other bits in register 0x009, the ETMTECR1, to 0 - * set all bits in register 0x007, the ETMTECR2, to 0 - * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). - */ - config->enable_ctrl1 = BIT(24); - config->enable_ctrl2 = 0x0; - config->enable_event = ETM_HARD_WIRE_RES_A; -} - static void etm_init_trace_id(struct etm_drvdata *drvdata) { /* @@ -674,7 +665,7 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) } etm_init_trace_id(drvdata); - etm_init_default_data(&drvdata->config); + etm_set_default(&drvdata->config); desc->type = CORESIGHT_DEV_TYPE_SOURCE; desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;