| Message ID | 1453354002-28366-13-git-send-email-wens@csie.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jan 21, 2016 at 01:26:39PM +0800, Chen-Yu Tsai wrote: > sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA > trigger levels can be increased. Also, the mmc module clock parent > has a higher clock rate, and the sample and output delay phases > are different. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Applied, thanks! Does that count as a fix, or does the A80 board can safely operate without it? Thanks, Maxime
On Sat, Jan 23, 2016 at 4:44 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Thu, Jan 21, 2016 at 01:26:39PM +0800, Chen-Yu Tsai wrote: >> sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA >> trigger levels can be increased. Also, the mmc module clock parent >> has a higher clock rate, and the sample and output delay phases >> are different. >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> > > Applied, thanks! > > Does that count as a fix, or does the A80 board can safely operate > without it? The compatible was added in v4.3, in commit 51424b286067 ("mmc: sunxi: Fix clk-delay settings"). I've not tested using the old compatibles with 50/52 MHz DDR. They do work just fine with the transfer modes we already supported. Either way its been there for a while so i don't see any need to pick it out as a fix. ChenYu
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index e838f206f2a0..f4f61b02be1a 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -543,7 +543,7 @@ }; mmc0: mmc@01c0f000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c0f000 0x1000>; clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>, <&mmc0_clk 1>, <&mmc0_clk 2>; @@ -557,7 +557,7 @@ }; mmc1: mmc@01c10000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c10000 0x1000>; clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>, <&mmc1_clk 1>, <&mmc1_clk 2>; @@ -571,7 +571,7 @@ }; mmc2: mmc@01c11000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c11000 0x1000>; clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>, <&mmc2_clk 1>, <&mmc2_clk 2>; @@ -585,7 +585,7 @@ }; mmc3: mmc@01c12000 { - compatible = "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c12000 0x1000>; clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>, <&mmc3_clk 1>, <&mmc3_clk 2>;
sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA trigger levels can be increased. Also, the mmc module clock parent has a higher clock rate, and the sample and output delay phases are different. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm/boot/dts/sun9i-a80.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)