From patchwork Mon Feb 1 07:58:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 8176591 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C6DBC9F4DD for ; Mon, 1 Feb 2016 08:03:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E4CD320426 for ; Mon, 1 Feb 2016 08:03:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D70E2041E for ; Mon, 1 Feb 2016 08:03:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aQ9QM-0000ex-B1; Mon, 01 Feb 2016 08:01:26 +0000 Received: from mail-pf0-x22e.google.com ([2607:f8b0:400e:c00::22e]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aQ9Pc-0000AW-5z for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2016 08:00:43 +0000 Received: by mail-pf0-x22e.google.com with SMTP id n128so78822374pfn.3 for ; Mon, 01 Feb 2016 00:00:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=Q3qq7ddYfdPF6Q5DINBlF/B7Z8oYwOxgJzpLphjbrwBXwLula0YyrqP6XcG3NmU191 TmkrWKwcFyXLnoqkW6ZsLP4aXRY53uKHEozpf/IKY9X32vLcU8t1XfAjKYZPUz2lnaKL WIsepJegLeC2rFB+5Qb6QAqyM3evJ8P1phNsY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=TJqkWXX6RaC1z6QnI1bkzsSge9UeSUnMYe1vQoDOxZJHaVmvCfZ44v7wayojRL+Nd0 wpLbvhvbbL2b4rOOgiD6QVK/poN2p7AqntqumflJI2cu+zbvhsA1gdpO0KD8954WhMZl sFLuA91CaxaGb+vfs8gIvLbP4UT1P7u/tw0zT/BCcd66XonKKebUCvG53VGyBBTfnkCc uMe2Ua9+tXfN+oAIeVeWONwKa/gvIuTtJTMsP+wmN0l3+dMoCwKxRs/Mi+m2n/6zQWWq 7/8aM40wCxXxCHk36Be5dpTYvFgZcxuGTEvdPY5DOoMxqmda4bGA5JKdq07OI5Wcz7FB Secw== X-Gm-Message-State: AG10YOQ8QlCXcbXwR69GYgQpYInH0DAZJ1oj/A9sreLlQDld0/KTZLplV4Ca68tNycoePWQs X-Received: by 10.98.68.220 with SMTP id m89mr36006412pfi.65.1454313619535; Mon, 01 Feb 2016 00:00:19 -0800 (PST) Received: from zcy-ubuntu.spreadtrum.com ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id o4sm40799282pfa.85.2016.02.01.00.00.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 01 Feb 2016 00:00:18 -0800 (PST) From: Chunyan Zhang To: mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com Subject: [PATCH 5/6] coresight-stm: Bindings for System Trace Macrocell Date: Mon, 1 Feb 2016 15:58:48 +0800 Message-Id: <1454313529-8860-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454313529-8860-1-git-send-email-zhang.chunyan@linaro.org> References: <1454313529-8860-1-git-send-email-zhang.chunyan@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160201_000040_467121_4326356F X-CRM114-Status: GOOD ( 11.37 ) X-Spam-Score: -1.4 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, linux-api@vger.kernel.orgi, corbet@lwn.net, zhang.lyra@gmail.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, broonie@kernel.org, pratikp@codeaurora.org, nicolas.guion@st.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mathieu Poirier The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier Acked-by: Rob Herring Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 62938eb..93147c0c 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -19,6 +19,7 @@ its hardware characteristcs. - "arm,coresight-etm3x", "arm,primecell"; - "arm,coresight-etm4x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -36,6 +37,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -202,3 +211,22 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name.