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Tue, 2 Feb 2016 10:01:47 +0000 From: Bai Ping To: , Subject: [PATCH V3 5/5] ARM: imx: Add msl code support for imx6qp Date: Tue, 2 Feb 2016 18:01:38 +0800 Message-ID: <1454407298-15545-5-git-send-email-ping.bai@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454407298-15545-1-git-send-email-ping.bai@nxp.com> References: <1454407298-15545-1-git-send-email-ping.bai@nxp.com> MIME-Version: 1.0 X-Originating-IP: [123.151.195.53] X-ClientProxiedBy: SG2PR03CA0076.apcprd03.prod.outlook.com (2a01:111:e400:5bb6::44) To AM3PR04MB532.eurprd04.prod.outlook.com (2a01:111:e400:8825::19) X-Microsoft-Exchange-Diagnostics: 1; AM3PR04MB532; 2:i08DR5/jehuy94bG7mEKfUSfGmgaCwCtVEjo8xPGtBwBiDnMjKXRd1rk6JTHK0wzX3kAR20wzpMddO1Kxq/rX3CZ7jEEucveQRJ/sYz0NOq8ouEU/5kzpNKbzlTHGWFYxZrmxZ+THj5o6GcorNgTsQ==; 3:4PD9jGZEaZvccpY2Hn6TQ5vPb3YhBJbcye8NRRIWvqkVhdKriio+3lu5nCs1ywawScQxFSiYDgMxePWRHMqo5OWawKZ7Ks6YEf7CShbhI0yzwj00G92gcn+uPF+thnKb; 25:lsZQJXApgemmWsUEHa1bcJPqZY15lUxxeqBS5PcidE8D054dpKMecQNEt159h0SqaoCcD717NfzrgCtsEU0fPqA0PYlf6FWkZdBTeQPtGuEBjm1oWfHv408t2X+J4mR8x3cY+kZ1TqCr9THTJJPsnLv+P65mx1RuHZDD+YyyjZ9Ls9QyfKZJQ1Q65X7eRc3ZRT1Qt7iqWzX8EJya9x7amF7wJGSIq0Jc8vH4jIoRMmj36AuDrwzMTboWQ7BAC+Np X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM3PR04MB532; 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AM3PR04MB532; 5:QCDQLf9V5GO3IzgrZ9agYoRCseWhA91/0g+Y9Tpj0GX6odDCQfmrFQOp8oxKzgjFJCkUH2gU5kxzN8CZc4m7QHF9qrjtdevX4RfsuVqrcIfiOX8autRvKhg4XEpDjidh77bgf7/ZhVt1eqN3cvj2Fg==; 24:d/VX0kbfCeAlbDCMk49yGr1ib77FyXSF6s0oFSct+kNmHrbyyllDK1oNhZZaC2G1RcM23gIa5MsL9c05fLMZpTuVgvPfXgr1aa99AODceMc= SpamDiagnosticOutput: 1:23 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2016 10:01:47.1103 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB532 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160202_020225_176499_CA825EC6 X-CRM114-Status: GOOD ( 12.18 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, pawel.moll@arm.com, mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, jacky.baip@gmail.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The i.MX6QP is a different SOC, but internally we treate it as i.MX6Q Rev_2.0 to maximum the code reusability. The chip silicon number we read from the ANADIG_DIGPROG is 0x630100. This patch add code to identify it as i.MX6QP Rev_1.0 when print out the silicon version. Signed-off-by: Bai Ping --- change for V3: -- add comment for the revision trick code arch/arm/mach-imx/anatop.c | 9 ++++++++- arch/arm/mach-imx/mach-imx6q.c | 8 ++++++-- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 231bb25..0f624d1 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -129,7 +129,14 @@ void __init imx_init_revision_from_anatop(void) switch (digprog & 0xff) { case 0: - revision = IMX_CHIP_REVISION_1_0; + /* + * For i.MX6QP, most of the code for i.MX6Q can be resued, + * so internally, we identify it as i.MX6Q Rev 2.0 + */ + if (digprog >> 8 & 0x01) + revision = IMX_CHIP_REVISION_2_0; + else + revision = IMX_CHIP_REVISION_1_0; break; case 1: revision = IMX_CHIP_REVISION_1_1; diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 3878494b..cb27d56 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -266,8 +266,11 @@ static void __init imx6q_init_machine(void) { struct device *parent; - imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", - imx_get_soc_revision()); + if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) + imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0); + else + imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", + imx_get_soc_revision()); parent = imx_soc_device_init(); if (parent == NULL) @@ -399,6 +402,7 @@ static void __init imx6q_init_irq(void) static const char * const imx6q_dt_compat[] __initconst = { "fsl,imx6dl", "fsl,imx6q", + "fsl,imx6qp", NULL, };