From patchwork Tue Feb 2 21:21:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Adamski X-Patchwork-Id: 8195741 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7C8D5BEEE5 for ; Tue, 2 Feb 2016 21:24:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B4A17200E3 for ; Tue, 2 Feb 2016 21:24:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DE54B2034E for ; Tue, 2 Feb 2016 21:24:53 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aQiQ4-0002aO-5t; Tue, 02 Feb 2016 21:23:28 +0000 Received: from box2.japko.eu ([91.121.152.53]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aQiPt-0002E0-Cx for linux-arm-kernel@lists.infradead.org; Tue, 02 Feb 2016 21:23:21 +0000 Received: by box2.japko.eu (Postfix, from userid 1000) id 2E1A262822; Tue, 2 Feb 2016 22:22:55 +0100 (CET) From: Krzysztof Adamski To: Linus Walleij , Maxime Ripard , Chen-Yu Tsai , Rob Herring , Hans de Goede , Vishnu Patekar , Krzysztof Adamski , Jens Kuske , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com Subject: [PATCH v2 2/5] dts: sun8i-h3: Add APB0 related clocks and resets Date: Tue, 2 Feb 2016 22:21:50 +0100 Message-Id: <1454448113-18810-3-git-send-email-k@japko.eu> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1454448113-18810-1-git-send-email-k@japko.eu> References: <1454448113-18810-1-git-send-email-k@japko.eu> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160202_132318_087222_0C091EDB X-CRM114-Status: UNSURE ( 7.67 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.3 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP APB0 is bearly mentioned in H3 User Manual and it is only setup in the Allwinners kernel dump for CIR. I have verified experimentally that the gate for R_PIO exists and works, though. There are probably other gates there but I don't know their order right now and I don't have access to their peripherals on my board to test them. Signed-off-by: Krzysztof Adamski --- arch/arm/boot/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 1524130e..ce35e93 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -276,6 +276,32 @@ clocks = <&osc24M>, <&pll6 1>, <&pll5>; clock-output-names = "mbus"; }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc24M>, <&osc32k>; + clock-output-names = "ahb0"; + }; + + apb0: clk@01f0140c { + compatible = "allwinner,sun8i-a23-apb0-clk"; + reg = <0x01f0140c 0x4>; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: clk@01f01428 { + compatible = "allwinner,sun8i-h3-abp0-gates-clk"; + reg = <0x01f01428 0x4>; + #clock-cells = <1>; + clocks = <&apb0>; + clock-indices = <0>, <1>; + clock-output-names = "apb0_pio", "apb0_ir"; + }; }; soc { @@ -493,5 +519,11 @@ interrupts = , ; }; + + apb0_reset: reset@01f014b0 { + reg = <0x01f014b0 0x4>; + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; }; };