From patchwork Wed Feb 3 08:15:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 8199131 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id EA4779F37A for ; Wed, 3 Feb 2016 08:19:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0F6A920204 for ; Wed, 3 Feb 2016 08:19:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 37D4E201FA for ; Wed, 3 Feb 2016 08:19:23 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aQsdK-0007Re-96; Wed, 03 Feb 2016 08:17:50 +0000 Received: from mail-pf0-x22b.google.com ([2607:f8b0:400e:c00::22b]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aQsce-0006ew-9q for linux-arm-kernel@lists.infradead.org; Wed, 03 Feb 2016 08:17:11 +0000 Received: by mail-pf0-x22b.google.com with SMTP id n128so9814517pfn.3 for ; Wed, 03 Feb 2016 00:16:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=Y2rrewJi5+b9JVFYpZfDeaeVqi+LjKOriVGQ+DDbHrymkW1OA10JL5GWWTUJCgIGsi LrWmhLMHssiRGwrUocc77aWoJlhUj5U4MokTgHbRMEdR2Qm4lKtMo5CyI6vObeugjoJF BC8ikXfmhtpTiR4J9a58QresEl3zmRKYcGeXA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JPMkKb/ZNkjTmppkRAdYf23PWZMo/NFHNJm5LC5Eug8=; b=HvpjvJNL0jP/YTqBcsfXvmq3Sk+rkqQTHflQ+GHpNW8TXskGr9kEQCOL7jceVd/4St Sr39M1SlD2ZAAdd0qZqz1wykBtgDfXJ77ID33UfyhgJj84Fzc6A4CF5mUDpR7BUaJ91g RaNcp0fhH7oskLK9PxJS/mmVFfKoo5m2YtGEKf2OQ5juxjQx0UR4BCJdR+TVTor9/8JE UtDBX9GDNv6fUuDMIRQKoa4cExgqXk0BdTkANjTUugGF620EseHLfbwfXtd5qU8qct9V nBuGYBPzRlGy3AnPaz4dTCJaeK8cmZnFWOnluv+29c3gs/zdplT3brOBbSzPtzrDsSPD Dn/Q== X-Gm-Message-State: AG10YOSeuc6l0PjaqBu+l1tXeFJ2b8fPnrlskB0VOVwicgo5zTqDssZgD0iXR4zhZdhbnDkL X-Received: by 10.98.72.215 with SMTP id q84mr310366pfi.152.1454487407364; Wed, 03 Feb 2016 00:16:47 -0800 (PST) Received: from zcy-ubuntu.spreadtrum.com ([175.111.195.49]) by smtp.gmail.com with ESMTPSA id tp6sm7725820pab.25.2016.02.03.00.16.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 03 Feb 2016 00:16:46 -0800 (PST) From: Chunyan Zhang To: mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com Subject: [PATCH V2 5/6] coresight-stm: Bindings for System Trace Macrocell Date: Wed, 3 Feb 2016 16:15:36 +0800 Message-Id: <1454487337-30184-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454487337-30184-1-git-send-email-zhang.chunyan@linaro.org> References: <1454487337-30184-1-git-send-email-zhang.chunyan@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160203_001708_711152_1BF61D27 X-CRM114-Status: GOOD ( 11.16 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, al.grant@arm.com, corbet@lwn.net, zhang.lyra@gmail.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tor@ti.com, broonie@kernel.org, mike.leach@arm.com, linux-api@vger.kernel.org, pratikp@codeaurora.org, nicolas.guion@st.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mathieu Poirier The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier Acked-by: Rob Herring Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/arm/coresight.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 62938eb..93147c0c 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -19,6 +19,7 @@ its hardware characteristcs. - "arm,coresight-etm3x", "arm,primecell"; - "arm,coresight-etm4x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. @@ -36,6 +37,14 @@ its hardware characteristcs. layout using the generic DT graph presentation found in "bindings/graph.txt". +* Additional required properties for System Trace Macrocells (STM): + * reg: along with the physical base address and length of the register + set as described above, another entry is required to describe the + mapping of the extended stimulus port area. + + * reg-names: the only acceptable values are "stm-base" and + "stm-stimulus-base", each corresponding to the areas defined in "reg". + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: @@ -202,3 +211,22 @@ Example: }; }; }; + +4. STM + stm@20100000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x20100000 0 0x1000>, + <0 0x28000000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + port { + stm_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port2>; + }; + }; + }; + +[1]. There is currently two version of STM: STM32 and STM500. Both +have the same HW interface and as such don't need an explicit binding name.