From patchwork Tue Feb 9 21:16:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Daney X-Patchwork-Id: 8265791 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 82AD3BEEE5 for ; Tue, 9 Feb 2016 21:20:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 98AE32017E for ; Tue, 9 Feb 2016 21:20:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7AE5920145 for ; Tue, 9 Feb 2016 21:20:04 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTFeq-0003Cr-FA; Tue, 09 Feb 2016 21:17:12 +0000 Received: from mail-pa0-x242.google.com ([2607:f8b0:400e:c03::242]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTFen-0003BN-1Q for linux-arm-kernel@lists.infradead.org; Tue, 09 Feb 2016 21:17:09 +0000 Received: by mail-pa0-x242.google.com with SMTP id sv5so4351852pab.3 for ; Tue, 09 Feb 2016 13:16:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=fvsru9/WSF7se62y4U1ZnC/6nx66G4so39tQ9PmQOhw=; b=zmNg4opCwkqWWoVeK82lO6P2QhdkNz2z0qSgWCQ9t3cP9+y7iA7Mj3onZnd5P/0M8Y BfYY8ccM7gG7JmNZvvvCnMZxUL6ATQSTvKObfAqIGX67iB1xLSqJBpTzZaQk5urzwKOx WzHrsuhjMfoYT/PCoDJs1Ta3xY2YGY4xITmzv2hffzp/ATyACyg4afL+9OYpZEdanoqZ 353sowd82My8qfCqJJirBgBDKh8OpM4XIaa0wAe8w2QMWCeHIRGSv2LEoYTyxD0IWMfm 9iPrWuDMNhmvPeZc/BtSRlrPspIjILKCvL4BGuQcSsilxH4hRb9vpDD+3JuC9bsGd8Bg bMig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=fvsru9/WSF7se62y4U1ZnC/6nx66G4so39tQ9PmQOhw=; b=mY6JrEBEEMFxWM2Mms1fHONZOLDL5Bm/MUR0r3PE2QdEgyGwXnbSJqmcbwkchACsSN TJT2FV1w79OnuzvEmfvP7u+rmJ9IioJhErW3nQg0WJs+/00T+pK2PJQmVvtIPs2JVlIw Vz7ensYsziHQB3cAmaE0KpX1DbdQJn/6uVDgep5peccotqxd8icwwZFQA4i0C8rBfbJT AjDgaTf/FFMDQp//QMat8UTtfu9II2rU1qxHWT+JKITgEPDhmZHFp/OZPj05TJirvZC2 UuUiwMFX9f6tm4pXtjyPbpbLRk6RH8OjLjTKaZgaTlidDwizjdEdNyVh/4P937eU+wmm LdDA== X-Gm-Message-State: AG10YOQeNaUPMYDG7CD7vWppZCmxT3D3Q0ut51y2C2ZRhezUlwRtaPoUuRYH2zclkB/3iw== X-Received: by 10.66.141.165 with SMTP id rp5mr53719520pab.56.1455052607174; Tue, 09 Feb 2016 13:16:47 -0800 (PST) Received: from dl.caveonetworks.com ([64.2.3.194]) by smtp.gmail.com with ESMTPSA id h66sm52587060pfd.91.2016.02.09.13.16.45 (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 09 Feb 2016 13:16:45 -0800 (PST) Received: from dl.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dl.caveonetworks.com (8.14.5/8.14.5) with ESMTP id u19LGi1t011452; Tue, 9 Feb 2016 13:16:44 -0800 Received: (from ddaney@localhost) by dl.caveonetworks.com (8.14.5/8.14.5/Submit) id u19LGerR011450; Tue, 9 Feb 2016 13:16:40 -0800 From: David Daney To: Will Deacon , linux-arm-kernel@lists.infradead.org, Mark Rutland , Catalin Marinas , Marc Zyngier Subject: [PATCH v2] arm64: Add workaround for Cavium erratum 27456 Date: Tue, 9 Feb 2016 13:16:39 -0800 Message-Id: <1455052599-11418-1-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.11.7 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160209_131709_132861_F7D24F3C X-CRM114-Status: GOOD ( 17.55 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Daney , linux-kernel@vger.kernel.org, Andrew Pinski MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Andrew Pinski On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become invalid if it contains data for a non-current ASID. This patch implements the workaround (which flushes the local icache when switching the mm) by using code patching. Signed-off-by: Andrew Pinski Signed-off-by: David Daney --- Changes from v1: Add entry to silicon-errata.txt Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 11 +++++++++++ arch/arm64/include/asm/cpufeature.h | 3 ++- arch/arm64/kernel/cpu_errata.c | 9 +++++++++ arch/arm64/mm/proc.S | 12 ++++++++++++ 5 files changed, 35 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 58b71dd..ba4b6ac 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -56,3 +56,4 @@ stable kernels. | | | | | | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | +| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 8cc6228..a969970 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -432,6 +432,17 @@ config CAVIUM_ERRATUM_23154 If unsure, say Y. +config CAVIUM_ERRATUM_27456 + bool "Cavium erratum 27456: Broadcast TLBI instructions may cause the icache to become invalid" + default y + help + On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI + instructions may cause the icache to become invalid if it + contains data for a non-current ASID. The fix is to flush + the icache when changing the mm context. + + If unsure, say Y. + endmenu diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 8f271b8..8136afc 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -30,8 +30,9 @@ #define ARM64_HAS_LSE_ATOMICS 5 #define ARM64_WORKAROUND_CAVIUM_23154 6 #define ARM64_WORKAROUND_834220 7 +#define ARM64_WORKAROUND_CAVIUM_27456 8 -#define ARM64_NCAPS 8 +#define ARM64_NCAPS 9 #ifndef __ASSEMBLY__ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index feb6b4e..a3e846a 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -100,6 +100,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01), }, #endif +#ifdef CONFIG_CAVIUM_ERRATUM_27456 + { + /* Cavium ThunderX, T88 pass 1.x - 2.1 */ + .desc = "Cavium erratum 27456", + .capability = ARM64_WORKAROUND_CAVIUM_27456, + MIDR_RANGE(MIDR_THUNDERX, 0x00, + (1 << MIDR_VARIANT_SHIFT) | 1), + }, +#endif { } }; diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index c164d2c..0f3be00 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include "proc-macros.S" @@ -137,7 +139,17 @@ ENTRY(cpu_do_switch_mm) bfi x0, x1, #48, #16 // set the ASID msr ttbr0_el1, x0 // set TTBR0 isb +alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 ret + nop + nop + nop +alternative_else + ic iallu + dsb nsh + isb + ret +alternative_endif ENDPROC(cpu_do_switch_mm) /*