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Tue, 09 Feb 2016 22:15:50 +0000 Received: from mail-bl2on0094.outbound.protection.outlook.com ([65.55.169.94] helo=na01-bl2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTGZW-0001GQ-IV for linux-arm-kernel@lists.infradead.org; Tue, 09 Feb 2016 22:15:48 +0000 Authentication-Results: linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=none action=none header.from=caviumnetworks.com; Received: from tiru-pc.caveonetworks.com (64.2.3.194) by BLUPR0701MB1780.namprd07.prod.outlook.com (10.162.87.150) with Microsoft SMTP Server (TLS) id 15.1.403.16; Tue, 9 Feb 2016 22:15:23 +0000 From: To: , Subject: [PATCH V2] arm64: KVM: Configure TCR_EL2.ps at runtime Date: Tue, 9 Feb 2016 14:15:13 -0800 Message-ID: <1455056113-25948-1-git-send-email-tchalamarla@caviumnetworks.com> X-Mailer: git-send-email 2.1.0 MIME-Version: 1.0 X-Originating-IP: [64.2.3.194] X-ClientProxiedBy: BY1PR13CA0040.namprd13.prod.outlook.com (25.162.107.178) To BLUPR0701MB1780.namprd07.prod.outlook.com (25.162.87.150) X-Microsoft-Exchange-Diagnostics: 1; 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X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tchalamarla@caviumnetworks.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAD_ENC_HEADER,BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tirumalesh Chalamarla Setting TCR_EL2.ps to 40 bits is wrong on systems with ps size is less than 40 bits. and with systems where RAM is at higher address, this will break KVM. This patch sets TCR_EL2.ps at runtime similar to VTCR_EL.ps Signed-off-by: Tirumalesh Chalamarla --- arch/arm64/include/asm/kvm_arm.h | 5 ++++- arch/arm64/kvm/hyp-init.S | 10 ++++++---- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 738a95f..92f2ffd 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -107,7 +107,10 @@ #define TCR_EL2_MASK (TCR_EL2_TG0 | TCR_EL2_SH0 | \ TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ) -#define TCR_EL2_FLAGS (TCR_EL2_RES1 | TCR_EL2_PS_40B) +/* + * TCR_EL2.ps is configured at runtime similar to VTCR_EL2 + */ +#define TCR_EL2_FLAGS (TCR_EL2_RES1) /* VTCR_EL2 Registers bits */ #define VTCR_EL2_RES1 (1 << 31) diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S index 3e568dc..b246de1e 100644 --- a/arch/arm64/kvm/hyp-init.S +++ b/arch/arm64/kvm/hyp-init.S @@ -85,15 +85,17 @@ __do_hyp_init: ldr_l x5, idmap_t0sz bfi x4, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH #endif - msr tcr_el2, x4 - - ldr x4, =VTCR_EL2_FLAGS /* * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in - * VTCR_EL2. + * TCR_EL2 and VTCR_EL2. */ mrs x5, ID_AA64MMFR0_EL1 bfi x4, x5, #16, #3 + + msr tcr_el2, x4 + + ldr x4, =VTCR_EL2_FLAGS + bfi x4, x5, #16, #3 /* * Read the VMIDBits bits from ID_AA64MMFR1_EL1 and set the VS bit in * VTCR_EL2.