From patchwork Thu Feb 11 18:40:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 8284411 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B2FADBEEE5 for ; Thu, 11 Feb 2016 18:51:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A29D420364 for ; Thu, 11 Feb 2016 18:51:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AA362202FE for ; Thu, 11 Feb 2016 18:51:01 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTwI1-0005wM-Sa; Thu, 11 Feb 2016 18:48:29 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aTwAr-00069f-1P for linux-arm-kernel@lists.infradead.org; Thu, 11 Feb 2016 18:41:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D6CA628; Thu, 11 Feb 2016 10:39:58 -0800 (PST) Received: from approximate.cambridge.arm.com (approximate.cambridge.arm.com [10.1.209.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8CEC73F21A; Thu, 11 Feb 2016 10:40:44 -0800 (PST) From: Marc Zyngier To: Catalin Marinas , Will Deacon , Mark Rutland , Christoffer Dall Subject: [PATCH v4 23/23] arm64: Panic when VHE and non VHE CPUs coexist Date: Thu, 11 Feb 2016 18:40:04 +0000 Message-Id: <1455216004-19499-24-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1455216004-19499-1-git-send-email-marc.zyngier@arm.com> References: <1455216004-19499-1-git-send-email-marc.zyngier@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160211_104105_413206_A735E245 X-CRM114-Status: GOOD ( 12.31 ) X-Spam-Score: -7.1 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Having both VHE and non-VHE capable CPUs in the same system is likely to be a recipe for disaster. If the boot CPU has VHE, but a secondary is not, we won't be able to downgrade and run the kernel at EL1. Add CPU hotplug to the mix, and this produces a terrifying mess. Let's solve the problem once and for all. If you mix VHE and non-VHE CPUs in the same system, you deserve to loose, and this patch makes sure you don't get a chance. This is implemented by storing the kernel execution level in a global variable. Secondaries will park themselves in a WFI loop if they observe a mismatch. Also, the primary CPU will detect that the secondary CPU has died on a mismatched execution level. Panic will follow. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/virt.h | 17 +++++++++++++++++ arch/arm64/kernel/head.S | 22 ++++++++++++++++++++++ arch/arm64/kernel/smp.c | 3 +++ 3 files changed, 42 insertions(+) diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h index 9f22dd6..f81a345 100644 --- a/arch/arm64/include/asm/virt.h +++ b/arch/arm64/include/asm/virt.h @@ -36,6 +36,11 @@ */ extern u32 __boot_cpu_mode[2]; +/* + * __run_cpu_mode records the mode the boot CPU uses for the kernel. + */ +extern u32 __run_cpu_mode[2]; + void __hyp_set_vectors(phys_addr_t phys_vector_base); phys_addr_t __hyp_get_vectors(void); @@ -60,6 +65,18 @@ static inline bool is_kernel_in_hyp_mode(void) return el == CurrentEL_EL2; } +static inline bool is_kernel_mode_mismatched(void) +{ + /* + * A mismatched CPU will have written its own CurrentEL in + * __run_cpu_mode[1] (initially set to zero) after failing to + * match the value in __run_cpu_mode[0]. Thus, a non-zero + * value in __run_cpu_mode[1] is enough to detect the + * pathological case. + */ + return !!ACCESS_ONCE(__run_cpu_mode[1]); +} + /* The section containing the hypervisor text */ extern char __hyp_text_start[]; extern char __hyp_text_end[]; diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 6f2f377..eb2ba55 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -578,7 +578,26 @@ ENTRY(set_cpu_boot_mode_flag) 1: str w20, [x1] // This CPU has booted in EL1 dmb sy dc ivac, x1 // Invalidate potentially stale cache line + adr_l x1, __run_cpu_mode + ldr w0, [x1] + mrs x20, CurrentEL + cbz x0, skip_el_check + cmp x0, x20 + bne mismatched_el ret +skip_el_check: // Only the first CPU gets to set the rule + str w20, [x1] + dmb sy + dc ivac, x1 // Invalidate potentially stale cache line + dsb sy + ret +mismatched_el: + str w20, [x1, #4] + dmb sy + dc ivac, x1 // Invalidate potentially stale cache line + dsb sy +1: wfi + b 1b ENDPROC(set_cpu_boot_mode_flag) /* @@ -593,6 +612,9 @@ ENDPROC(set_cpu_boot_mode_flag) ENTRY(__boot_cpu_mode) .long BOOT_CPU_MODE_EL2 .long BOOT_CPU_MODE_EL1 +ENTRY(__run_cpu_mode) + .long 0 + .long 0 .popsection /* diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index b1adc51..bc7650a 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -113,6 +113,9 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) pr_crit("CPU%u: failed to come online\n", cpu); ret = -EIO; } + + if (is_kernel_mode_mismatched()) + panic("CPU%u: incompatible execution level", cpu); } else { pr_err("CPU%u: failed to boot: %d\n", cpu, ret); }