diff mbox

[5/6] dt-bindings: add documentation of rk3399 clock controller

Message ID 1455674089-16567-1-git-send-email-jay.xu@rock-chips.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jianqun Xu Feb. 17, 2016, 1:54 a.m. UTC
From: Xing Zheng <zhengxing@rock-chips.com>

Add the devicetree binding for the cru on the rk3399 which quite
similar structured as previous clock controllers.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
 .../bindings/clock/rockchip,rk3399-cru.txt         | 82 ++++++++++++++++++++++
 1 file changed, 82 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt

Comments

Rob Herring (Arm) Feb. 18, 2016, 2:36 p.m. UTC | #1
On Wed, Feb 17, 2016 at 09:54:49AM +0800, jianqun.xu wrote:
> From: Xing Zheng <zhengxing@rock-chips.com>
> 
> Add the devicetree binding for the cru on the rk3399 which quite
> similar structured as previous clock controllers.
> 
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> ---
>  .../bindings/clock/rockchip,rk3399-cru.txt         | 82 ++++++++++++++++++++++
>  1 file changed, 82 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
> new file mode 100644
> index 0000000..07bcc6e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
> @@ -0,0 +1,82 @@
> +* Rockchip RK3399 Clock and Reset Unit

[...]

> +Example: General Register Files
> +
> +	pmugrf: syscon@ff320000 {
> +		compatible = "rockchip,rk3399-pmugrf", "syscon";

Is this documented?

> +		reg = <0x0 0xff320000 0x0 0x1000>;
> +	};
> +
> +	grf: syscon@ff770000 {
> +		compatible = "rockchip,rk3399-grf", "syscon";

ditto.

> +		reg = <0x0 0xff770000 0x0 0x10000>;
> +	};
> +
> +Example: Clock controller node:
> +
> +	pmucru: pmu-clock-controller@ff750000 {
> +		compatible = "rockchip,rk3399-pmucru";
> +		reg = <0x0 0xff750000 0x0 0x1000>;
> +		#clock-cells = <1>;
> +		#reset-cells = <1>;
> +	};
> +
> +	cru: clock-controller@ff760000 {
> +		compatible = "rockchip,rk3399-cru";
> +		reg = <0x0 0xff760000 0x0 0x1000>;
> +		rockchip,grf = <&grf>;
> +		#clock-cells = <1>;
> +		#reset-cells = <1>;
> +	};
> +
> +Example: UART controller node that consumes the clock generated by the clock
> +  controller:
> +
> +	uart0: serial@ff1a0000 {
> +		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
> +		reg = <0x0 0xff180000 0x0 0x100>;
> +		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
> +		clock-names = "baudclk", "apb_pclk";
> +		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> +		reg-shift = <2>;
> +		reg-io-width = <4>;
> +	};
> -- 
> 1.9.1
> 
>
Jianqun Xu Feb. 19, 2016, 12:48 a.m. UTC | #2
Hi Rob

? 18/02/2016 22:36, Rob Herring ??:
> On Wed, Feb 17, 2016 at 09:54:49AM +0800, jianqun.xu wrote:
>> From: Xing Zheng <zhengxing@rock-chips.com>
>>
>> Add the devicetree binding for the cru on the rk3399 which quite
>> similar structured as previous clock controllers.
>>
>> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
>> ---
>>   .../bindings/clock/rockchip,rk3399-cru.txt         | 82 ++++++++++++++++++++++
>>   1 file changed, 82 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
>> new file mode 100644
>> index 0000000..07bcc6e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
>> @@ -0,0 +1,82 @@
>> +* Rockchip RK3399 Clock and Reset Unit
>
> [...]
>
>> +Example: General Register Files
>> +
>> +	pmugrf: syscon@ff320000 {
>> +		compatible = "rockchip,rk3399-pmugrf", "syscon";
>
> Is this documented?
Since there is no documentation for rockchip grf from early SoCs, I 
think if we need to add a new devicetree documentation, such as
Documentation/devicetree/bindings/clock/rockchip,rk3399-grf.txt ?

If you agree, I will add it in next patch

>
>> +		reg = <0x0 0xff320000 0x0 0x1000>;
>> +	};
>> +
>> +	grf: syscon@ff770000 {
>> +		compatible = "rockchip,rk3399-grf", "syscon";
>
> ditto.
>
>> +		reg = <0x0 0xff770000 0x0 0x10000>;
>> +	};
>> +
>> +Example: Clock controller node:
>> +
>> +	pmucru: pmu-clock-controller@ff750000 {
>> +		compatible = "rockchip,rk3399-pmucru";
>> +		reg = <0x0 0xff750000 0x0 0x1000>;
>> +		#clock-cells = <1>;
>> +		#reset-cells = <1>;
>> +	};
>> +
>> +	cru: clock-controller@ff760000 {
>> +		compatible = "rockchip,rk3399-cru";
>> +		reg = <0x0 0xff760000 0x0 0x1000>;
>> +		rockchip,grf = <&grf>;
>> +		#clock-cells = <1>;
>> +		#reset-cells = <1>;
>> +	};
>> +
>> +Example: UART controller node that consumes the clock generated by the clock
>> +  controller:
>> +
>> +	uart0: serial@ff1a0000 {
>> +		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
>> +		reg = <0x0 0xff180000 0x0 0x100>;
>> +		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
>> +		clock-names = "baudclk", "apb_pclk";
>> +		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
>> +		reg-shift = <2>;
>> +		reg-io-width = <4>;
>> +	};
>> --
>> 1.9.1
>>
>>
>
>
>
Heiko Stuebner Feb. 19, 2016, 12:53 a.m. UTC | #3
Am Freitag, 19. Februar 2016, 08:48:15 schrieb Jianqun Xu:
> Hi Rob
> 
> ? 18/02/2016 22:36, Rob Herring ??:
> > On Wed, Feb 17, 2016 at 09:54:49AM +0800, jianqun.xu wrote:
> >> From: Xing Zheng <zhengxing@rock-chips.com>
> >> 
> >> Add the devicetree binding for the cru on the rk3399 which quite
> >> similar structured as previous clock controllers.
> >> 
> >> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> >> ---
> >> 
> >>   .../bindings/clock/rockchip,rk3399-cru.txt         | 82
> >>   ++++++++++++++++++++++ 1 file changed, 82 insertions(+)
> >>   create mode 100644
> >>   Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt>> 
> >> diff --git
> >> a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
> >> b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new
> >> file mode 100644
> >> index 0000000..07bcc6e
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
> >> @@ -0,0 +1,82 @@
> >> +* Rockchip RK3399 Clock and Reset Unit
> > 
> > [...]
> > 
> >> +Example: General Register Files
> >> +
> >> +	pmugrf: syscon@ff320000 {
> >> +		compatible = "rockchip,rk3399-pmugrf", "syscon";
> > 
> > Is this documented?
> 
> Since there is no documentation for rockchip grf from early SoCs, I
> think if we need to add a new devicetree documentation, such as
> Documentation/devicetree/bindings/clock/rockchip,rk3399-grf.txt ?

The grf is not clock-specific, so the directory is probably not correct.
I'd think bindings/arm/rockchip/grf.txt might be better or
bindings/soc/rockchip/grf.txt or somewhere else. And define the properties 
for all per-soc GRFs in there.

In any case we really should add the missing grf binding documentation (in a 
separate patch of course), as the grf is a pretty commonly used shared 
component.


> 
> If you agree, I will add it in next patch
> 
> >> +		reg = <0x0 0xff320000 0x0 0x1000>;
> >> +	};
> >> +
> >> +	grf: syscon@ff770000 {
> >> +		compatible = "rockchip,rk3399-grf", "syscon";
> > 
> > ditto.
> > 
> >> +		reg = <0x0 0xff770000 0x0 0x10000>;
> >> +	};
> >> +
> >> +Example: Clock controller node:
> >> +
> >> +	pmucru: pmu-clock-controller@ff750000 {
> >> +		compatible = "rockchip,rk3399-pmucru";
> >> +		reg = <0x0 0xff750000 0x0 0x1000>;
> >> +		#clock-cells = <1>;
> >> +		#reset-cells = <1>;
> >> +	};
> >> +
> >> +	cru: clock-controller@ff760000 {
> >> +		compatible = "rockchip,rk3399-cru";
> >> +		reg = <0x0 0xff760000 0x0 0x1000>;
> >> +		rockchip,grf = <&grf>;
> >> +		#clock-cells = <1>;
> >> +		#reset-cells = <1>;
> >> +	};
> >> +
> >> +Example: UART controller node that consumes the clock generated by the
> >> clock +  controller:
> >> +
> >> +	uart0: serial@ff1a0000 {
> >> +		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
> >> +		reg = <0x0 0xff180000 0x0 0x100>;
> >> +		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
> >> +		clock-names = "baudclk", "apb_pclk";
> >> +		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> >> +		reg-shift = <2>;
> >> +		reg-io-width = <4>;
> >> +	};
> >> --
> >> 1.9.1
Jianqun Xu Feb. 19, 2016, 1:05 a.m. UTC | #4
Hi Heiko

? 19/02/2016 08:53, Heiko Stuebner ??:
> Am Freitag, 19. Februar 2016, 08:48:15 schrieb Jianqun Xu:
>> Hi Rob
>>
>> ? 18/02/2016 22:36, Rob Herring ??:
>>> On Wed, Feb 17, 2016 at 09:54:49AM +0800, jianqun.xu wrote:
>>>> From: Xing Zheng <zhengxing@rock-chips.com>
>>>>
>>>> Add the devicetree binding for the cru on the rk3399 which quite
>>>> similar structured as previous clock controllers.
>>>>
>>>> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
>>>> ---
>>>>
>>>>    .../bindings/clock/rockchip,rk3399-cru.txt         | 82
>>>>    ++++++++++++++++++++++ 1 file changed, 82 insertions(+)
>>>>    create mode 100644
>>>>    Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
>>>> b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new
>>>> file mode 100644
>>>> index 0000000..07bcc6e
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
>>>> @@ -0,0 +1,82 @@
>>>> +* Rockchip RK3399 Clock and Reset Unit
>>>
>>> [...]
>>>
>>>> +Example: General Register Files
>>>> +
>>>> +	pmugrf: syscon@ff320000 {
>>>> +		compatible = "rockchip,rk3399-pmugrf", "syscon";
>>>
>>> Is this documented?
>>
>> Since there is no documentation for rockchip grf from early SoCs, I
>> think if we need to add a new devicetree documentation, such as
>> Documentation/devicetree/bindings/clock/rockchip,rk3399-grf.txt ?
>
> The grf is not clock-specific, so the directory is probably not correct.
> I'd think bindings/arm/rockchip/grf.txt might be better or
> bindings/soc/rockchip/grf.txt or somewhere else. And define the properties
> for all per-soc GRFs in there.
>
> In any case we really should add the missing grf binding documentation (in a
> separate patch of course), as the grf is a pretty commonly used shared
> component.
>
Got it, I will add bindings/soc/rockchip/grf.txt in next patch
Thanks !
>
>>
>> If you agree, I will add it in next patch
>>
>>>> +		reg = <0x0 0xff320000 0x0 0x1000>;
>>>> +	};
>>>> +
>>>> +	grf: syscon@ff770000 {
>>>> +		compatible = "rockchip,rk3399-grf", "syscon";
>>>
>>> ditto.
>>>
>>>> +		reg = <0x0 0xff770000 0x0 0x10000>;
>>>> +	};
>>>> +
>>>> +Example: Clock controller node:
>>>> +
>>>> +	pmucru: pmu-clock-controller@ff750000 {
>>>> +		compatible = "rockchip,rk3399-pmucru";
>>>> +		reg = <0x0 0xff750000 0x0 0x1000>;
>>>> +		#clock-cells = <1>;
>>>> +		#reset-cells = <1>;
>>>> +	};
>>>> +
>>>> +	cru: clock-controller@ff760000 {
>>>> +		compatible = "rockchip,rk3399-cru";
>>>> +		reg = <0x0 0xff760000 0x0 0x1000>;
>>>> +		rockchip,grf = <&grf>;
>>>> +		#clock-cells = <1>;
>>>> +		#reset-cells = <1>;
>>>> +	};
>>>> +
>>>> +Example: UART controller node that consumes the clock generated by the
>>>> clock +  controller:
>>>> +
>>>> +	uart0: serial@ff1a0000 {
>>>> +		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
>>>> +		reg = <0x0 0xff180000 0x0 0x100>;
>>>> +		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
>>>> +		clock-names = "baudclk", "apb_pclk";
>>>> +		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
>>>> +		reg-shift = <2>;
>>>> +		reg-io-width = <4>;
>>>> +	};
>>>> --
>>>> 1.9.1
>
>
>
>
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
new file mode 100644
index 0000000..07bcc6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -0,0 +1,82 @@ 
+* Rockchip RK3399 Clock and Reset Unit
+
+The RK3399 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
+- compatible: CRU should be "rockchip,rk3399-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_isp" - external ISP clock - optional,
+ - "ext_jtag" - external JTAG clock - optional
+ - "ext_vip" - external VIP clock - optional,
+ - "usbotg_out" - output clock of the pll in the otg phy
+
+Example: General Register Files
+
+	pmugrf: syscon@ff320000 {
+		compatible = "rockchip,rk3399-pmugrf", "syscon";
+		reg = <0x0 0xff320000 0x0 0x1000>;
+	};
+
+	grf: syscon@ff770000 {
+		compatible = "rockchip,rk3399-grf", "syscon";
+		reg = <0x0 0xff770000 0x0 0x10000>;
+	};
+
+Example: Clock controller node:
+
+	pmucru: pmu-clock-controller@ff750000 {
+		compatible = "rockchip,rk3399-pmucru";
+		reg = <0x0 0xff750000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	cru: clock-controller@ff760000 {
+		compatible = "rockchip,rk3399-cru";
+		reg = <0x0 0xff760000 0x0 0x1000>;
+		rockchip,grf = <&grf>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+	uart0: serial@ff1a0000 {
+		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xff180000 0x0 0x100>;
+		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+		clock-names = "baudclk", "apb_pclk";
+		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+	};