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Wed, 17 Feb 2016 02:13:01 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id u1H2Cvpl020177; Tue, 16 Feb 2016 19:12:58 -0700 From: Mingkai Hu To: Subject: [PATCH v3] dts/ls2080a: Update PCIe compatible Date: Wed, 17 Feb 2016 10:04:23 +0800 Message-ID: <1455674663-9273-1-git-send-email-Mingkai.Hu@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BN1AFFO11FD025; 1:o//Man6/Z4DLin1uGb8KQ3cZ9hvOJAi48qytc63UNas25x865/8dkYPvzVO4sbtgvNSLgNtcLA1ohZjoH05GVcmVpsUeh1kecL8N4jZFLQafDkXafv72d/5XBpZ3/bL2L1SybNSO5PE4S0po9kinLmAvVwVwFenAlBDTCZWv3lVftBE4WkQvxZZlcJfmDSxCGnglyR26OTmyGp2QD4PmNCqBTSqQRxCl/M0obatcY2oxtkFjBp7KpoGavaf8VdaR4iLHvCSOIkRlJSK5ri9+QxsrYB8c7a/96CatLiu/DSqNhzHzHU1zsaed36JOSxBtRm8HzN4WCMkv+JvKt/ftsb9ppgllSfaY/88YrsMvhuWmIMnikzOR5SaIcbFB3u6FQw06xA+1wu8Oeab4I4AmzGNCcLVxaGYxmuOH0DG9Av4= X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; 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Signed-off-by: Minghuan Lian Signed-off-by: Mingkai Hu Acked-by: Rob Herring --- v3: - Make the compatible consistent between layerscape-pci.txt and dts file. v2: - Rebased to latest kernel base Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index e376785..ef683b2 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -14,7 +14,7 @@ information. Required properties: - compatible: should contain the platform identifier such as: "fsl,ls1021a-pcie", "snps,dw-pcie" - "fsl,ls2080a-pcie", "snps,dw-pcie" + "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" - reg: base addresses and lengths of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 2b23d03..1b18d7a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -456,7 +456,8 @@ }; pcie@3400000 { - compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", + "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; @@ -479,7 +480,8 @@ }; pcie@3500000 { - compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", + "snps,dw-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; @@ -502,7 +504,8 @@ }; pcie@3600000 { - compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", + "snps,dw-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; @@ -525,7 +528,8 @@ }; pcie@3700000 { - compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", + "snps,dw-pcie"; reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config";